Lucent Technologies Inc.

Other

Zeljko Zilic

Richard G Stuby, Jr

Lucian Remus Albu

Barry K Britton

Wai-Bor Leung

James A Thompson

Ho Trong Nguyen

Gary P Powell

William B Andrews

The invention provides an input/output (I/O) signaling voltage range discriminator (and corresponding method) which is used to control a configurable logic device such as a configurable I/O buffer in a second electronic circuit in response to a detected signaling voltage range of a first electronic circuit. The discriminator outputs an indication of the signaling voltage range of the first electronic circuit to a configurable I/O buffer enabling it to adapt to the signaling levels used by the first electronic circuit. The I/O buffer, based on the indication provided by the discriminator, can then configure its logic to become tolerant and/or compatible with digital signals transferred to and from the first electronic circuit.

Signaling voltage range discriminator

A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can be programmed during PLD operations, without reconfiguring the PLD.

Programmable clock manager for a programmable logic device that can be

A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least one output clock and the PCM can perform one or more delay-locked loop (DLL) functions. In one embodiment, the DLL functions include clock delay, duty-cycle adjustment, and clock doubling, where duty-cycle adjustment can optionally be applied independently to the doubled clock cycles.

Programmable clock manager for a programmable logic device that can

A programmable logic device (PLD), such as a field programmable gate array (FPGA), has a programmable clock manager (PCM) that converts an input clock into at least two different output clocks having different clock rates. The different output clocks can be used to control different processes either within or outside the FPGA. For example, one output clock can be used to control the FPGA's input/output registers, while a second, faster output clock can be used to control the FPGA's internal registers.

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Allentown, PA, United States of America

Zeljko Zilic