Apple Inc.

Zelin Zhang

Winnie W Yeung

Leela Kishore Kothamasu

Guanlan Xu

Eddie M Robinson

Benjiman L Goodman

Yoong Chert Foo

Jonathan M Redshaw

Cheng Li

David K Li

Hungse Cha

Techniques are disclosed relating to graphics processor data caches. In some embodiments, datapath executes instructions that operate on input operands from architectural registers. Data cache circuitry caches architectural register data for the datapath circuitry. Scoreboard circuitry tracks, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry and a pointer to the entry of the data cache circuitry. Tiered scoreboard circuitry and data storage circuitry may be implemented (e.g., to provide fast scoreboard access for active threads and to give a landing spot for long-latency data retrieval operations). Various disclosed techniques may improve cache performance, reduce power consumption, reduce area, or some combination thereof.

Scoreboard for register data cache

Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

Cache control to preserve register data

Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Snapshot arbitration techniques for memory requests

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San Jose, CA, United States of America

Zelin Zhang