Intel Corporation

Zelig Wayner

Tsvika Kurts

Tommy Bojan

Amit Gradstein

Ittai Anati

Gila Kamhi

Marcelo Yuffe

Thierry Pons

Noam Yosef

Yoad Yagil

Ranan Fraer

Embodiments of the present invention provide a processor having an inactive state of operation and methods thereof. The processor, according to some demonstrative embodiments of the invention, the processor may include a controller to determine an inactive state of operation is to be entered, and to cause a predetermined set of one or more execution units to execute a predetermined sequence of one or more micro-operations prior to entering the inactive state. Other embodiments are described and claimed.

Processor having inactive state of operation and method thereof

A value to better match a termination circuit to a characteristic impedance of a bus signal line is determined. A determination is also made as to when a bus, that includes the line and that is being used by a bus agent in its normal mode of operation, will be available for adjusting the termination circuit in a Quiet Cycle, based at least on knowledge of the bus protocol and tracking of certain bus protocol events. The termination circuit is adjusted according to the determined value, during the Quiet Cycle.

Apparatus and method for bus signal termination compensation during detected quiet cycle

A circuit for driving and receiving signals on a bus line includes a pull-up switch and a pull-down switch. The pull-up switch has an impedance that matches the characteristic impedance of the bus line. The pull-down switch has an impedance of about half of the characteristic impedance of the bus line. When the circuit is receiving a signal or driving a logic high signal on the bus line, the pull-up switch is enabled so that the bus line voltage is pulled up, while the pull-down switch is disabled to prevent the pull-down switch from pulling down the bus line voltage. When the circuit is driving a logic low signal on the bus line, the pull-down switch is enabled so that the bus line voltage is pulled down, while the pull-up switch is disabled to prevent the pull-up switch from pulling up the bus line voltage.

Method and apparatus for driving a signal using switchable on-die termination

An input buffer to interface between a main logic circuit and a peripheral device, which includes a first transistor that is adapted to be coupled to a first voltage supply and a first terminal, is described. A second transistor, which is adapted to be coupled to a second voltage supply and said terminal, is also included. The input buffer includes a first logic circuit to limit the amount of voltage applied to the first and second enable terminals of the first and second transistors. The first logic circuit is adapted to be coupled to a second terminal, the first enable terminal, and the second enable terminal. A second logic circuit, designed to limit the amount of voltage applied to the first terminal, is also included. The second logic circuit is coupled to the input terminals of the first and second transistors, as well as the first terminal. A method for buffering a signal received from a peripheral component includes receiving a first signal from a peripheral component. The voltage level of the first signal is reduced, and it is applied to the enable terminals of a first and a second transistor. A second signal is applied to an output terminal, and the voltage level of the second signal is limited. The second signal is then transmitted to an internal component.

Input buffer for a mixed voltage environment

An output buffer to serve as an interface between a main logic circuit and a peripheral device is described. The output buffer includes a first transistor adapted to be coupled to a first voltage supply and an output terminal. The first transistor is designed to charge the output terminal to a first state. A pull-down network to charge the output terminal to a second state is also included. The pull-down network is adapted to be coupled between the output terminal and a second voltage supply and is designed for alternate operation with the first transistor. The output buffer also includes a logic circuit to enable the first transistor and the pull-down network. The logic circuit is coupled to an enable terminal of the first transistor, the pull-down network, the first voltage supply, and the second voltage supply.

Output buffer for a mixed voltage environment

An input buffer to interface among devices on a main circuit board is described. The input buffer includes a first transistor coupled between a first terminal and an input terminal of an inverter. The first transistor has an enable terminal adapted to be coupled to a first voltage supply. A second transistor that is coupled between the first terminal and the input terminal is also included. The input buffer further includes a control circuit to enable the second transistor. The control circuit is coupled to the first terminal, an enable terminal of the second transistor, the input terminal, and an output terminal of the inverter. A method for buffering signals among devices on a main circuit board comprises receiving a first signal in a first state from a first device. A first portion of the first signal is transmitted through a first transistor. A second portion of the first signal is transmitted through a second transistor. A second signal is generated by applying the first signal to the enable terminals of the third and fourth transistors. The second signal is then transmitted to a second device.

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Haifa, Israel

Zelig Wayner