Advasense Technologies Ltd.

Pixim Israel Ltd

Zeituni Golan

Noam Eshel

Vladimir Koifman

A device that includes a pixel array, an interfacing circuit and a sample and hold circuit. The interfacing circuit directs to at least one pixel of the pixel array a sampled voltage that is outputted from the sample and hold circuit. The sample and hold circuit includes an NMOS transistor, a bootstrap circuit, a capacitor, sample phase switches and hold phase switches. During the sample phase the source of the NMOS transistor receives the input voltage; the gate of the NMIS transistor receives, from the bootstrap circuit a gate voltage that exceeds a supply voltage and a capacitor of the sample and hold circuit is charged to the input voltage to provide the sampled voltage. During a hold phase the capacitor stores the sampled voltage; the gate, source and drain of the NMOS transistor are maintained at the same potential and the source of the NMOS transistor is disconnected from an input port through which the input voltage was provided.

Device and method for providing a reference signal

A device that includes a pixel array and a sample and hold circuit configured to provide sampled current to the pixel array wherein the sample and hold circuit includes a first transistor, a capacitor and a pair of current mirrors. The pair of current minors are connected to the first transistor and wherein the capacitor is connected to a drain of the first transistor. The sample and hold circuit is configured to sample an input current during a sampling phase to provide a sampled current, wherein the sampling includes: providing the input current to the pair of current mirrors and allowing the capacitor to be charged to the capacitor voltage that is a function of the input current; store, during a hold phase, the capacitor voltage; wherein the capacitor voltage forces an output stage of the sample and hold circuit to output a current that is substantially equal to the sampled current; and utilize the pair of current mirrors to force the gate, source and drain voltages of the first transistor to be equal to each other during the hold phase.

A system that includes: multiple transistors that comprise a first transistor that is maintained in a weak inversion state; wherein sources of the multiple transistors are coupled to a low current source; wherein drains of the multiple transistors are coupled to a voltage supply source; a first amplifier that has a positive input, negative input and an output; wherein the positive input receives an input voltage; wherein the negative input is coupled to a source of the first transistor; wherein the output is coupled to a gate of the first transistor and to a multiplication and subtracting circuit; a multiplication and subtraction circuit that is coupled to the first amplifier and outputs an output signal that equals a difference between the input voltage and a product of a current reduction variable and a voltage reduction signal; wherein the voltage reduction signal is associated with a current reduction factor; wherein the output signal is provided to a second transistor that is maintained in weak inversion; and wherein the second transistor outputs, in response to a reception of the output signal, a current that is responsive to the pixel output signal, is proportional to the low current and is inversely proportional to the current reduction variable and the current reduction factor.

Growing community of inventors

Kfar Saba, Israel

Zeituni Golan