International Business Machines Corporation

Barcelona Supercomputing Center-centro Nacional De Supercomputacion

Barcelona Supercomputing Center

Zehra Noman Sura

John Kevin O'Brien

Tong Chen

Tao Zhang

Alexandre E Eichenberger

Carlo Bertolli

Marc Gonzalez Tallada

Kathryn Mary O'Brien

Olivier H Sallenave

Michael K Gschwind

Valentina Salapura

Ravi Nair

Parijat Dube

John Kevin Patrick O'Brien

John K P O'Brien

Ashish Kundu

Hans Mikael Jacobson

Krishnan Kunjunny Kailas

Daniel Arthur Prener

Diana Jeanne Arroyo

Arpith C Jacob

Priya Ashok Nagpurkar

Stefania Costache

Gauri Joshi

Byoungro So

Eduard Ayguade

Xavier Martorell

Rajiv Alazhath Ravindran

Li Feng Zhang

Arun Kwangil Iyengar

Mukesh Kumar Mohania

Bishwaranjan Bhattacharjee

Lixin Zhang

Yaoqing Gao

Qi Zhang

Gong Su

Hoang Tam Vo

Wenqi Cao

Kevin K O'Brien

Techniques for estimating runtimes of one or more machine learning tasks are provided. For example, one or more embodiments described herein can regard a system that can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an extraction component that can extract a parameter from a machine learning task. The parameter can define a performance characteristic of the machine learning task. Also, the computer executable components can comprise a model component that can generate a model based on the parameter. Further, the computer executable components can comprise an estimation component that can generate an estimated runtime of the machine learning task based on the model. The estimated runtime can define a period of time beginning at an initiation of the machine learning task and ending at a completion of the machine learning task.

Runtime estimation for machine learning tasks

Methods and systems for optimizing an application for a computing system having multiple distinct memory locations that are interconnected by one or more communication channels include determining one or more data handling properties for a data region in an application. One or more data handling policies for the data region are determined based on the one or more data handling properties. Data setup costs are determined for a scope in the application that uses the data region in different memory locations based on the one or more data handling properties. The application is optimized in accordance with the one or more data handling policies and the data setup costs for the different memory locations.

Flexible optimized data handling in systems with multiple memories

Embodiments for implementing mixed precision learning for neural networks by a processor. A neural network may be replicated into a plurality of replicated instances and each of the plurality of replicated instances differ in precision used for representing and determining parameters of the neural network. Data instances may be routed to one or more of the plurality of replicated instances for processing according to a data pre-processing operation.

Data driven mixed precision learning for neural networks

An example operation may include one or more of generating a proposal to perform a ledger operation at a first node, informing one or more second nodes of the proposal, receiving a decision on consensus among the first node and the one or more second nodes for the proposal, and performing the ledger operation at the first node when there is consensus, wherein the ledger operation changes a state database of a ledger of the first node and wherein the state database corresponds to a blockchain stored in the ledger.

Index management for a database

A method for transparently moving a block of memory with respect to an application using the block of memory, includes inserting, by a compiler, in an application that includes a memory allocation call, instructions for transparently moving a block of memory with respect to an application using the block of memory. The instructions include obtaining a first pointer returned by a memory allocator, where the first pointer points to an internal data structure, the internal data structure includes a read-write lock and a second pointer, and the second pointer points to an actual memory block. The instructions further include acquiring a read lock on a read-write lock in the internal data structure, before the first pointer is used by the application, obtaining the second pointer to the actual memory block, and dereferencing the second pointer to access the actual memory block for the application data.

Reducing fragmentation of computer memory

Embodiments for implementing partial synchronization between compute processes based on threshold specification in a computing environment. One or more compute processes may be synchronized in one of a plurality of types of computing platforms using a barrier having a barrier release condition based on a threshold of one or more measures. The barrier is defined according to one or more parameters. The one or more compute processes may be released via the barrier upon exceeding the threshold of the one or more measures.

Partial synchronization between compute tasks based on threshold specification in a computing system

A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.

Optimizing branch re-wiring in a software instruction cache

According to one embodiment, a method of creating compiler-generated memory mapping hints in a computer system includes analyzing code, by a compiler of the computer system, to identify data access patterns in the code. System configuration information defining data processing system characteristics of a target system for the code is accessed. The data processing system characteristics include a plurality of processing resources and memory domain characteristics relative to the processing resources. A preferred allocation of data in memory domains of the target system is determined based on mapping the code to one or more selected processing resources and mapping the data to one or more of the memory domains based on the memory domain characteristics relative to the one or more selected processing resources. The preferred allocation is stored as compiler-generated memory mapping hints in a format accessible by a physical memory mapping resource of the target system.

Compiler-generated memory mapping hints

In one embodiment, a computer-implemented method includes receiving source code to be compiled into an executable file for an unaligned instruction set architecture (ISA). Aligned assembled code is generated, by a computer processor. The aligned assembled code complies with an aligned ISA and includes aligned processor code for a processor and aligned accelerator code for an accelerator. A first linking pass is performed on the aligned assembled code, including relocating a first relocation target in the aligned accelerator code that refers to a first object outside the aligned accelerator code. Unaligned assembled code is generated in accordance with the unaligned ISA and includes unaligned accelerator code for the accelerator and unaligned processor code for the processor. A second linking pass is performed on the unaligned assembled code, including relocating a second relocation target outside the unaligned accelerator code that refers to an object in the unaligned accelerator code.

Unaligned instruction relocation

Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.

Method to efficiently implement synchronization using software managed address translation

Embodiments relate to program structure-based blocking. An aspect includes receiving source code corresponding to a computer program by a compiler of a computer system. Another aspect includes determining a prefetching section in the source code by a marking module of the compiler. Yet another aspect includes performing, by a blocking module of the compiler, blocking of instructions located in the prefetching section into instruction blocks, such that the instruction blocks of the prefetching section only contain instructions that are located in the prefetching section.

Program structure-based blocking

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Yorktown Heights, NY, United States of America

Zehra Noman Sura