Intel Corporation

Other

Zeev Sperber

Robert Valentine

Mark Jay Charney

Elmoustapha Ould-Ahmed-Vall

Alexander F Heinecke

Jesus Corbal

Menachem Adelman

Stanislav Shwartsman

Dan Baum

Igor Yanover

Christopher J Hughes

Vinodh Gopal

Rajesh Poornachandran

Amit Gradstein

Simon Rubanovich

Bret L Toll

Raanan Sade

Benny Eitan

Milind Baburao Girkar

Barukh Ziv

Ronen Zohar

Mark J Buxton

Koby Gottlieb

Rajiv Kapoor

Doron Orenstein

Evangelos Georganas

Gabi Malka

Yuri Gebil

Rinat Rappoport

Ittai Anati

Lihu Rappoport

Shlomo Raikin

Cristina S Anderson

Seth Abraham

Jose Yallouz

Michael Mishaeli

Adi Yoaz

Ron Gabor

Ehud Cohen

Ofer Levy

Galina Ryvchin

Thierry Pons

Piotr Majcher

Sreenivas Subramoney

Jayesh Gaur

Mostafa Hagog

Gavri Berger

Wajdi K Feghali

Shay Gueron

Sean M Gulley

Naveen K Mellempudi

Jacob Doweck

Doron Orenstien

Franck Sala

Mohan J Kumar

Naveen Kumar

Shantanu R Gupta

Ganapati Srinivasa

Tsvika Kurts

Theodros Yigzaw

Jose Andy Vargas

Julius Yuli Mandelblat

Nadav Bonen

Hisham Shafi

Tal Uliel

Geeyarpuram N Santhanakrishnan

Vjekoslav Svilan

Gregory Pribush

Efraim Rotem

Jason W Brandt

Hong Wang

Nir Rosenzweig

Suleyman Sair

Vlad Krasnov

Mohammad A Abdallah

Shih-Lien L Lu

David J Sager

Avinash Sodani

Boris Ginzburg

Herbert H Hum

Srikanth T Srinivasan

Robert S Chappell

Ronak Singhal

Beeman C Strong

Ido Ouziel

Nilesh K Jain

Jared Warner Stark, Iv

Brinda Ganesh

George Leifman

Marius A Cornea-Hasegan

Itamar S Kazachinsky

Dhiraj D Kalamkar

Simcha Gochman

Asaf Rubinstein

Vijaykumar Balaram Kadgi

Binh Q Pham

Ziv Aviv

Nicolas I Kacevas

Arik Narkis

Bob Valentine

Embodiments systems for adaptive dynamic dispatch of micro-operations are disclosed. An embodiment includes redundant execution units; a dispatcher to dispatch micro-operations to the redundant execution units, the micro-operations having multiple micro-operation types; a first counter to generate a first count of dispatches, during a window, of micro-operations having a first type; a second counter to generate a second count of dispatches, during the window, of micro-operations having any type; control hardware to cause a switch between a first mode and a second mode based in part on the first count and the second count; and a dispatcher to, in the first mode, dispatch micro-operations having the first type to only a subset of the redundant execution units, and, in the second mode, is to dispatch micro-operations having the first type to all of the redundant execution units.

Adaptive dynamic dispatch of micro-operations

Disclosed embodiments relate to systems and methods for performing 8-bit floating-point vector dot product instructions. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of first source, second source, and destination vectors, the opcode to indicate execution circuitry is to multiply pairs of 8-bit floating-point formatted elements of the specified first and second sources, and accumulate the resulting products with previous contents of a corresponding single-precision element of the specified destination, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.

Systems and methods for performing 8-bit floating-point vector dot product instructions

Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.

Instructions to convert from FP16 to BF8

Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.

Matrix transpose and multiply

Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

Apparatuses, methods, and systems for hashing instructions

Techniques for scale and reduction of BF16 data elements are described. An exemplary instruction includes fields for an having fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of a packed data destination operand, wherein the opcode is to indicate that execution circuitry is to perform, for each data element position of the packed data source operands, a floating point scale operation of a BF16 data element of the first packed data source by multiplying the data element by a power of 2 value, wherein a value of the exponent of the power of 2 value is a floor value of a BF16 data element of the second packed data source, and store a result of the floating point scale operation into a corresponding data element position of the packed data destination operand.

BFLOAT16 scale and/or reduce instructions

Techniques for matrix multiplication are described. In some examples, decode circuitry is to decode a single instruction having fields for an opcode, an indication of a location of a first source operand, an indication of a location of a second source operand, and an indication of a location of a destination operand, wherein the opcode is to indicate that execution circuitry is to at least convert data elements of the first and second source operands from a first floating point representation to a second floating point representation, perform matrix multiplication with the converted data elements, and accumulate results of the matrix multiplication in the destination operand in the first floating point representation; and the execution circuitry is to execute to the decoded instruction as specified by the opcode.

Apparatuses, methods, and systems for instructions for matrix multiplication instructions

Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.

Systems, methods, and apparatuses for dot production operations

Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

Systems and methods for performing 16-bit floating-point matrix dot product instructions

Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.

Systems and methods to store a tile register pair to memory

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

Systems, methods, and apparatus for tile configuration

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address, and execution circuitry to execute the decoded instruction to store configuration information about usage of storage for two-dimensional data structures at the memory address.

Systems, methods, and apparatuses for matrix operations

Systems, methods, and apparatuses relating to instructions to convert 16-bit floating-point formats are described. In one embodiment, a processor includes fetch circuitry to fetch a single instruction having fields to specify an opcode and locations of a source vector comprising N plurality of 16-bit half-precision floating-point elements, and a destination vector to store N plurality of 16-bit bfloat floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the source vector from 16-bit half-precision floating-point format to 16-bit bfloat floating-point format and store each converted element into a corresponding location of the destination vector, decode circuitry to decode the fetched single instruction into a decoded single instruction, and the execution circuitry to respond to the decoded single instruction as specified by the opcode.

Apparatuses, methods, and systems for instructions to convert 16-bit floating-point formats

Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

Systems, methods, and apparatuses for matrix add, subtract, and multiply

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Zichron Yackov, Israel

Zeev Sperber