Intel Corporation

Daedalus Prime LLC

Daedauls Prime LLC

Zeev Offen

Inder M Sodhi

Altug Koker

Ryan Donovan Wells

Robert L Farrell

Ariel Berkovits

Thomas A Piazza

Opher D Kahn

Doron Rajwan

Nadav Shulman

Itai Feit

Alon Naveh

Ivan Herrera Mejia

Iris Sorani

Jason W Brandt

Sanjeev S Jahagirdar

Ittai Anati

Ron Gabor

Michael Mishaeli

Shlomo Raikin

Ken Drottar

Ehud Cohen

Ashish V Choubal

Julius Yuli Mandelblat

Larisa Novakovsky

Oded Lempel

Geeyarpuram N Santhanakrishnan

Itamar S Kazachinsky

Marc D Torrant

Michael J Muchnick

Amjad M Khan

Shalini Sharma

Michelle J Moravan

In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Controlling operating voltage of a processor

Controlling operating frequency of a processor

Embodiments including systems, methods, and apparatuses associated providing an interface between a north complex and a south complex of a system on a chip (SoC). In embodiments, the north complex may include a microcontroller in an input signal requirement. A power-on control block may be coupled with the microcontroller, and the power-on control block may be configured to receive a control signal from a component of the south complex, and alter the control signal based at least in part on the input signal requirement of the microcontroller.

Interface for communication between circuit blocks of an integrated circuit, and associated apparatuses, systems, and methods

A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.

Technique to share information among different cache coherency domains

Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation. During a context restore operation the system agent does not restore the context registers with saved context values that are equal to the reset value of the context register.

Context save and restore

In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core and agent and including a plurality of domains and a logic to receive isochronous parameter information from the agent and environmental information of a platform and to generate first and second values, and a power controller to control a frequency of the domains based at least in part on the first and second values. Other embodiments are described and claimed.

Independently controlling frequency of plurality of power domains in a processor system

Growing community of inventors

Folsom, CA, United States of America

Zeev Offen