Saifun Semiconductors Ltd.

Other

Infineon Technologies Flash Ltd.

Zeev Cohen

Eduardo Maayan

Ran Dvir

Boaz Eitan

Ilan Bloom

David Finzi

Mori Edan

A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.

Mass storage device architecture and operation

Apparatus including a virtual ground array, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. The virtual ground array includes at least one block of data, and peripheral circuitry adapted to simultaneously access a plurality of subsets of the at least one block of data stored in the memory cells along at least one word line. Methods for operating the virtual ground array in a mass storage device include simultaneously accessing a plurality of subsets of at least one block of data stored in the memory cells along at least one word line.

Mass storage array and methods for operation thereof

A method for operating a memory device, the method comprising marking a portion of a memory device associated with a group of bits comprising at least one bit upon which an operation is to be performed, and operating on the group of bits and skipping operating on at least one unmarked portion of the memory device in an operation cycle of the memory device. A random access memory (RAM) device is also disclosed comprising a plurality of addresses for storing therein data, and at least one address pointer for at least one of the addresses in the RAM device.

Look ahead methods and apparatus

A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Programming of nonvolatile memory cells

A flash memory card including a controller, at least one control pad, at least one memory, and a high voltage switch logic module in communication with the at least one control pad, the controller and the at least one memory, the high voltage switch logic module being adapted to selectively route voltage from the at least one control pad to one of the controller and the at least one memory. If the voltage input to the at least one control pad does not exceed a predefined level, then the voltage may be routed from the at least one control pad to the controller. If the voltage input to the at least one control pad exceeds the predefined level, then the voltage may be routed from the at least one control pad to the at least one memory.

High voltage insertion in flash memory cards

A method for defect detection, comprising providing a memory cell array comprising memory cells connected to word lines and local bit lines, and global bit lines connected to the local bit lines, the global bit lines comprising at least two portions, one portion connected to a voltage source, and the other portion connected to a defect detector, the defect detector comprising logic circuit components for outputting a logic signal, and detecting a defect comprising at least one of a short circuit and an open circuit in at least one of the word lines, local bit lines and global bit lines by detecting a signal at the defect detector. Embodiments of apparatus for carrying out the methods of the invention are also disclosed.

Defects detection

Disclosed is a method utilizing dynamic masking for efficiently programming an N-bit memory array and, more generally, for mapping successive subsets of data segments into a succession of N-bit auxiliary bytes. When the number of programming bits in an incoming byte exceeds K, a mask maps the bit pattern of the incoming byte into sequential N-bit auxiliary bytes. A first auxiliary byte retains the bit pattern of the incoming byte up to the Kth programming bit, and the remaining bit positions of the first auxiliary byte exhibit a state complementary to the programming bits. A second auxiliary byte retains the bit pattern of the incoming byte starting with the first location after the Kth programming bit and continuing up to the Kth additional programming bit (if any); all remaining bit positions of the second auxiliary byte (including the bit positions that contained programming bits in the first auxiliary byte) exhibit the complementary state. Further auxiliary bytes can be created to accommodate all K programming bits, if necessary.

Method and apparatus for dynamically masking an N-bit memory array having individually programmable cells

A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed of a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steeps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

A method for programming an array having a multiplicity of memory cells. The method includes, per cell to be programmed, verifying a programmed or non-programmed state of the cell and flagging those of the cells that verify as non-programmed during one of the verify steps after having previously verified as programmed. A programming pulse having a programming level is applied to the non-programmed cells which are not flagged cells. The steps of verifying, flagging and applying are then repeated until all of the cells verify as programmed at least once. Subsequently, a boost pulse having a boost programming level lower than the programming level is applied to the flagged cells.

Growing community of inventors

Safed, Israel

Zeev Cohen