Infineon Technologies Flash Gmbh & Co. Kg

Apple Inc.

Anobit Technologies Ltd.

Flometrica Ltd.

Zeev Cohen

Ofir Shalvi

Dotan Sokolov

Eyal Gurgi

Ariel Maislos

Gil Semo

Alon Marcu

Giacomo Curatolo

Rico Srowik

Meirav Raz

The present invention provides a handheld USB Cup for use in collection of a fluidic body sample, comprising ad receptacle comprising side surfaces, a bottom plate and a sensor assembly, the sensor assembly comprising at least one sensor and a slave circuitry; said sensor assembly is permanently affixed to said side surfaces or said bottom plate. The receptacle is capable of maintaining the fluidic body sample for a sufficient time period in the vicinity of the sensor thereby the sensor is operative to provide continuous measurement of an electric, chemical or physical property of the urine. The slave circuitry responds to the electric, chemical or physical property of the fluidic body sample received from the sensor and is configured and operable to electronically communicate the measurement of the electric, chemical or physical property of the fluidic body sample to an external processing master unit.

Disposable USB cup

A method for data storage in a memory that includes a plurality of analog memory cells includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Memory device with adaptive capacity

A method for data storage in a memory () that includes a plurality of analog memory cells () includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Memory Device with adaptive capacity

A method for operating a memory that includes multiple analog memory cells includes storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels. After storing the data, second storage values are read from at least some of the cells, including at least one interfered cell that belongs to a group of cells. A Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell is detected and canceled. The second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, are processed so as to reconstruct the data.

Reduction of back pattern dependency effects in memory devices

A method for storing data in a memory that includes a plurality of analog memory cells includes mapping the data to programming values, which are selected from a set of nominal programming values. The set of nominal programming values includes at least a first nominal programming value and a second nominal programming value, which is higher than the first nominal programming value. A part of the data is stored in the analog memory cells by programming at least a first group of the cells using the first nominal programming value. A statistical characteristic of the first group of the cells is measured after programming the first group of the cells using the first nominal programming value. The second nominal programming value is modified responsively to the statistical characteristic, and at least a second group of the cells is programmed using the modified second nominal programming value.

Adaptive programming of analog memory cells using statistical characteristics

A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.

Device with memory and method of operating device

Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells, the array comprising a multiplicity of array columns having at least one redundant column of non-volatile memory cells adapted to replace a defective array column, a column decoder, and a column redundancy unit. The column decoder is adapted to receive an address of a memory cell to which data is to be written or from which data is to be read. The column redundancy unit is adapted to decide whether the decoded address is to be written to or read from an array from or a redundant column. The data required by the column redundancy unit is stored in a column redundancy memory, which is connected to the column redundancy unit by means of a dedicated column redundancy bus.

Non-volatile semiconductor memory device and method for operating a non-volatile memory device

A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column redundancy structure is also arranged into an addressable first redundancy column and an addressable second redundancy column. A first column array which is found to be defective is replaced by mapping its address to the first redundancy column. In a similar manner, a second column array which is found to be defective is replaced by mapping its address to the second redundancy column.

Column redundancy reuse in memory devices

A programming element for programming data into a plurality of non-volatile memory cells of a non-volatile memory cell array, the data being transferred to the non-volatile memory cell array in a data word comprising a plurality of data items. The programming element comprises a detection element for detecting at least a first data word and a second data word which are to be transferred to the non-volatile memory cell array, a determination element for determining the number of data items in the first data word and the second data word that need a change of the state of a respective non-volatile memory cell, a comparator element for comparing the determined number of data items with a maximum number of programmable data items using one programming pulse, a data word merge control element for merging the first data word with the second data word into a merged data word to be programmed into the non-volatile memory cell array if the determined number is less or equal to the maximum number, wherein the merged data word is to be programmed into the non-volatile memory cells together using the same at least one programming pulse.

Non-volatile memory cell device, programming element and method for programming data into a plurality of non-volatile memory cells

The present invention is a method, circuit and system for storing bits on a Non-Volatile Memory ('NVM') array. According to some embodiments of the present invention, a bit scrambling block may rearrange the received block of bits according to a spreading pattern. An error correction code block may generate an error correction code ('ECC') based on either the original block of bits or based on the rearranged block of bits, and a data storing circuit may store in the NVM array the ECC and the block of bits from which the ECC was not derived.

Growing community of inventors

Zichron-Yaakov, Israel

Zeev Cohen