Qualcomm Incorporated

Ati Technologies Ulc

Zeeshan S Syed

Denis J Foley

Aris Balatsos

Serag M GadelRab

Bin Du

Milivoje M Aleksic

Carl K Mizuyabu

Fariborz Pourbigharaz

In a process, a power mode indicator is transmitted from a content server and is received by a Portable Communication Device (PCD). The indicator is indicative of a power mode potentially available to a circuit block in the PCD. The circuit block exhibits different levels of power consumption when operated in different power modes and is operated in the indicated power mode in response to the received power mode indicator. The content server may be a stream server. The circuit block may be operated in the power mode to receive/process a data stream.

Server initiated power mode switching in portable communication devices

The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.

Method and apparatus for securing digital information on an integrated circuit read only memory during test operating modes

The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

Method and apparatus for securing digital information on an integrated circuit during test operating modes

A technique for recording information in a battery operated device is provided such that quality level of the recorded information may be changed 'on the fly.' In one embodiment, while persistently recording information at a first quality level, the battery operated device may, in response to an input a desire or need to change recording quality level, thereafter persistently record the information at a second quality level different from the first quality level, without interrupting the continuity of the recording session. In a presently preferred embodiment, the information being recorded may comprise video information or audio information. Subsequent inputs indicating the need to change recording quality level yet again may also be received thereby causing the battery operated device to persistently record the information at yet another quality level, which quality level may be the same as the first quality level.

Method and apparatus for recording information in battery operated devices

A method and apparatus for detecting an error compares a hardwired reference value to a corresponding predetermined value and generates an error indication in response to a change in the predetermined value. In one embodiment, the predetermined value is set to be the same as the hardwired reference value and in response to an electrostatic discharge event or any other suitable cause of error, the predetermined value changes so that a comparison indicates that an error has occurred. An error indication is then generated which may be, for example, an interrupt to recovery logic that generates recovery control information to reset a functional block that was corrupted or to perform in an entire chip reset if desired.

Growing community of inventors

Markham, Canada

Zeeshan S Syed