Monolithic Power Systems, Inc.

Chengdu Monolithic Power Systems Co., Ltd.

Ze-Qiang Yao

Junjian Zhao

Heng Li

Suwei Wang

Liwei Hou

Ji-Hyoung Yoo

Yu-Huei Lee

Zheng Luo

Jeesung Jung

Tong Chen

Haifeng Yang

Fayou Yin

Xiaodan Shang

Integrated circuit ('IC') unit and a wafer for fabricating IC units. The wafer has a first surface and a second surface opposite to the first surface. A redistribution metal layer may be formed on the first surface and may be patterned to have a redistribution metal layer pattern. A backside metal layer may be formed on the second surface and patterned to have a backside metal layer pattern so that the backside metal layer may be adapted to generate a backside stress on the wafer to at least partially offset a front side stress generated by the redistribution metal layer on the wafer.

Integrated circuit unit and wafer with integrated circuit units

A LED driving system for driving a LED matrix. The LED driving system includes an interconnection structure having a first surface and a second surface opposite to the first surface and a plurality of driver dies/chips attached to the first surface of the interconnection structure. The LED matrix is divided into a plurality of sub LED matrix sections that are attached to the second surface of the interconnection structure. The interconnection structure is configured to electrically couple each one of the plurality of sub LED matrix sections to a corresponding one driver die/chip in the plurality of driver dies/chips.

LED matrix driving system

The present disclosure discloses a semiconductor device having conductive bumps formed on a conductive redistribution layer and associated method for manufacturing. The semiconductor device may further include a first type shallow trench formed on a passivation layer overlying a semiconductor substrate. The conductive redistribution layer is formed in the first type shallow trench. A polyimide layer may be formed between neighboring conductive redistribution layers should a plurality of the conductive redistribution layers are formed with or without the first type shallow trench formed for each of the plurality of conductive redistribution layers.

Semiconductor device having conductive bump with improved reliability

Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures.

Method for forming dual gate insulation layers and semiconductor device having dual gate insulation layers

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Santa Clara, CA, United States of America

Ze-Qiang Yao