Nvidia Corporation

Ze Long

Shirish C Gadre

Olivier Giroux

Ronny Krashinsky

Luke Durant

Jerome Francis Duluk, Jr

Jack H Choquette

Lacky V Shah

John H Edmondson

Manan Patel

Gentaro Hirota

Brian S Pharris

Ravi Kiran Manyam

Jeff Tuckey

Apoorv Parle

Wish Gandhi

Kyrylo Perelygin

Prakash Bangalore Prabhakar

Rajballav Dash

Steve Heinrich

Greg Palmer

Sandeep Navada

Eric Werness

Naman Govil

Shayani Deb

Wishwesh Anil Gandhi

Michael A Parker

Michael Murphy

David Fontaine

Harold Carter Edwards

Girish Bharambe

Hemayet Hossain

Rishkul Kulkarni

Debajit Bhattacharya

Maciej Marcin Piechotka

Cory Perry

Sebastian Piotr Jodlowski

Raphael Dominique Pierre Boissel

Anis Ladram

Isaac Gelado

Raymond Hoi Man Wong

Yashwardhan Narawane

Vikram Dhar

Apparatuses, systems, and techniques to cause to cause one or more first storage address sizes to be converted into one or more second storage address sizes. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more first storage address sizes to be converted to one or more second storage address sizes based, at least in part, on one or more identifiers of one or more physical storage locations corresponding to either of the one or more first storage address sizes or the one or more second storage address sizes.

Address size conversion via application programming interface

Apparatuses, systems, and techniques to enable a program to access data regardless of where said data is stored. In at least one embodiment, a system enables a program to access data regardless of where said data is stored, based on, for example, one or more locations encoding one or more addresses of said data.

Location agnostic data access

Various embodiments include a parallel processing computer system that provides multiple memory synchronization domains in a single parallel processor to reduce unneeded synchronization operations. During execution, one execution kernel may synchronize with one or more other execution kernels by processing outstanding memory references. The parallel processor tracks memory references for each domain to each portion of local and remote memory. During synchronization, the processor synchronizes the memory references for a specific domain while refraining from synchronizing memory references for other domains. As a result, synchronization operations between kernels complete in a reduced amount of time relative to prior approaches.

Thread synchronization across memory synchronization domains

A new level(s) of hierarchy—Cooperate Group Arrays (CGAs)—and an associated new hardware-based work distribution/execution model is described. A CGA is a grid of thread blocks (also referred to as cooperative thread arrays (CTAs)). CGAs provide co-scheduling, e.g., control over where CTAs are placed/executed in a processor (such as a GPU), relative to the memory required by an application and relative to each other. Hardware support for such CGAs guarantees concurrency and enables applications to see more data locality, reduced latency, and better synchronization between all the threads in tightly cooperating collections of CTAs programmably distributed across different (e.g., hierarchical) hardware domains or partitions.

Cooperative group arrays

Distributed shared memory (DSMEM) comprises blocks of memory that are distributed or scattered across a processor (such as a GPU). Threads executing on a processing core local to one memory block are able to access a memory block local to a different processing core. In one embodiment, shared access to these DSMEM allocations distributed across a collection of processing cores is implemented by communications between the processing cores. Such distributed shared memory provides very low latency memory access for processing cores located in proximity to the memory blocks, and also provides a way for more distant processing cores to also access the memory blocks in a manner and using interconnects that do not interfere with the processing cores' access to main or global memory such as hacked by an L2 cache. Such distributed shared memory supports cooperative parallelism and strong scaling across multiple processing cores by permitting data sharing and communications previously possible only within the same processing core.

Distributed shared memory

Apparatuses, systems, and techniques to execute programs in a single hardware context on a graphics processing unit (GPU). In at least one embodiment, resource management patches expressed in library or executable code are applied to one or more kernels to ensure execution in a shared context on a GPU.

Technique for sharing context among multiple threads

One embodiment sets forth a technique for dynamically allocating memory during multi-threaded program execution for a coprocessor that does not support dynamic memory allocation, memory paging, or memory swapping. The coprocessor allocates an amount of memory to a program as a put buffer before execution of the program begins. If, during execution of the program by the coprocessor, a request presented by a thread to store data in the put buffer cannot be satisfied because the put buffer is full, the thread notifies a worker thread. The worker thread processes a notification generated by the thread by dynamically allocating a swap buffer within a memory that cannot be accessed by the coprocessor. The worker thread then pages the put buffer into the swap buffer during execution of the program to empty the put buffer, thereby enabling threads executing on the coprocessor to dynamically receive memory allocations during execution of the program.

Virtual memory structure for coprocessors having memory allocation limitations

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San Jose, CA, United States of America

Ze Long