International Business Machines Corporation

Ze Gui Pang

Yu Wang

Ivan L Wemple

Wen Bao Yin

Charles S Chiu

Eric W Tremble

Kurt A Carlsen

Umberto Garofano

Xuan Zou

David Toub

Hai Tao Han

An integrated circuit design method, system and simulator, wherein the integrated circuit design method includes: determining a region in which power supply noise shall be analyzed; determining current model parameters of the region; determining model parameters of a power supply network model; inputting into a simulator a net list; judging whether or not the region satisfies noise requirements of a chip power supply; and if the region satisfies noise requirements of the chip power supply, determining that the initial area is a minimum area that satisfies the noise requirements of the chip power supply in case the initial number of decoupling capacitors are used in the region.

Integrated circuit design and simulation

Methods, systems, computer programs, etc., determine the required number of decoupling capacitors, and approximate locations for the decoupling capacitors, for a region of an integrated circuit. Switching elements of the region are entered into a simulation program running on a computerized device. Also, a power distribution model of the region is entered into the simulation program, and a power-supply voltage compression target is entered into the simulation program. These methods, systems, etc., generate an upper number of decoupling capacitors required to satisfy the compression target when all the switching elements concurrently switch. For each switching element, the methods, systems, etc., generate a specific number of decoupling capacitors required to satisfy the compression when only the element switches, calculate a fraction of the specific number to the upper number, assign the fraction of the total number of decoupling capacitors to each switching circuit element, and place the fraction of the total number of decoupling capacitors in electrical proximity to the element.

Early decoupling capacitor optimization method for hierarchical circuit design

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Shanghai, China

Ze Gui Pang