Adv Antest Corporation

Ze'ev Raz

Xinguo Zhang

Yang Liu

Alan S Krech, Jr

Edmundo De La Puente

Ken Hanh Duc Lai

Darrin Paul Albers

Yi Liu

Jesse Hobbs

Shigeo Chiyoda

Embodiments of the present invention utilize a dual buffer size threshold system for raising interrupts that allows DUT testing systems to perform real-time buffer memory allocation procedures in an on demand basis. Using dual interrupt threshold systems in the manner described by embodiments of the present invention, DUT testing systems can reduce the need to decide on a single buffer size threshold when testing a set of DUTs that separately provide different amounts of fail data relative to each other. As such, embodiments of the present invention can minimize the overhead processing spent on interrupt handling while also reducing the amount wait time needed for the data processing module to process fail data for each DUT. Thus, embodiments of the present invention can increase the use of tester resources more efficiently while decrease the amount of time a tester system spends collecting and/or analyzing fail data for a set of DUTs during a testing session.

Method and system for advanced fail data transfer mechanisms

System and method of selecting defective columns in NAND memory devices for repair. After locating the defective blocks and defective columns in a NAND memory device, a weight value is calculated for each defective block by dividing a total number of defective blocks that would be inherently repaired as a result of repairing the respective defective block by a number of defective data columns in the respective defective block. A defective block with the greatest weight value is selected for repair in which the defective columns in the selected block are substituted by redundant columns. Other defective blocks with defective columns having the same column addresses with the defective columns in the selected defective block are automatically selected for repair as well. Remaining defective columns are selected for repair by iteratively updating weight values and selecting a defective block that has the greatest weight value among the remaining defective blocks.

Method and apparatus for defect repair in NAND memory device

Automated testing system and method of testing memory devices with distributed processing operations. A redundancy analysis system includes multiple test site processors (TSPs) respectively coupled to multiple devices under test (DUTs). Each TSP is installed with a redundancy analyzer configured to analyzing redundancy data returned from a respective (DUT). Each TSP may be coupled with a respective fail engine for returning the redundancy data from the corresponding DUT. A main TSP of the multiple TSPs is configured to control testing routine over the multiple DUTs and process failure related data from the DUTs. The main TSP may direct the RAs distributed in the multiple TSPs to execute the redundancy analyzers in parallel.

Testing memory devices with distributed processing operations

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Ze'ev Raz