Mitsubishi Electric Corporation

Ze Chen

Katsumi Nakamura

Fumihito Masuoka

Koji Tanaka

Koichi Nishi

Tsuyoshi Kawakami

Yuki Haraguchi

Kenji Suzuki

Akihiko Furukawa

Kazuhiro Shimizu

Koji Sadamatsu

Akito Nishii

Yuji Murakami

Hayato Okamoto

An object of a technique of the present disclosure is to suppress reduction in withstand voltage in a power semiconductor device. A semiconductor base includes an n&#x2212; type semiconductor substrate and at least one p type diffusion layer formed separately from each other on a surface layer on a side of a first main surface of the semiconductor substrate in a terminal region. A power semiconductor device includes at least one insulating film formed on a first main surface of the semiconductor base between an insulating film and the insulating film. A semi-insulating film has contact with the insulating film on the insulating film, and has contact with the first main surface in at least two regions where the insulating film is not formed between the insulating films.

Power semiconductor device

Provided are a semiconductor device in which the lifetime of holes is controlled and the switching loss is suppressed, and a method of manufacturing the same. Provided are a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, a first buffer layer of the first conductive type provided between the drift layer and the second main surface in contact with the drift layer, having a resistivity lower than that of the drift layer, and having an impurity concentration higher than that of the drift layer, and a high resistivity layer provided between the first buffer layer and the second main surface and having a resistivity higher than that of the drift layer.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes: a semiconductor substrate including a front surface, a back surface that is opposite to the front surface, and a drift layer of a first conductive type disposed between the front surface and the back surface; a first diffusion layer of a second conductive type provided between the drift layer and the front surface; a second diffusion layer provided between the drift layer and the back surface; a first buffer layer of the first conductive type provided between the drift layer and the second diffusion layer, having a concentration higher than that of the drift layer, and into which a proton is injected; and a second buffer layer of the first conductive type provided between the first buffer layer and the second diffusion layer and having a concentration higher than that of the drift layer, wherein a peak concentration of the second buffer layer is higher than a peak concentration of the first buffer layer, an impurity concentration of the first buffer layer gradually decreases toward the back surface, a length from a peak position of the first buffer layer to a boundary between the drift layer and the first buffer layer is represented by Xa, a length from the peak position to a boundary between the first buffer layer and the second buffer layer is represented by Xb, and Xb&#x3e;5 Xa.

Semiconductor device and manufacturing method thereof

A semiconductor device includes an N-type drift layer provided between a first main surface and a second main surface of the semiconductor substrate and an N-type buffer layer provided between the N-type drift layer and the first main surface and having a higher impurity peak concentration than the N-type drift layer. The N-type buffer layer has a structure that a first buffer layer, a second buffer layer, a third buffer layer, and a fourth buffer layer are disposed in this order from a side of the first main surface. When a distance from an impurity peak position of the first buffer layer to an impurity peak position of the second buffer layer is L12 and a distance from an impurity peak position of the second buffer layer to an impurity peak position of the third buffer layer is L23, a relationship of L23/L12&#x2265;3.5 is satisfied.

Semiconductor device

Provided is a technique capable of improving performance of a semiconductor device. A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type located on the first semiconductor region, third and fourth semiconductor regions of the second conductivity type, a fifth semiconductor region of the first conductivity type, and an electrode. The third semiconductor region is located on the second semiconductor region, and has a higher impurity concentration than the second semiconductor region. The fourth semiconductor region has a higher impurity concentration than the second semiconductor region, is located separately from the third semiconductor region in a planar view, and has contact with the second semiconductor region. The fifth semiconductor region is located on the second semiconductor region, and is located between the third and fourth semiconductor regions in a planar view. The electrode does not have contact with the fourth and fifth semiconductor regions but has contact with the third semiconductor region.

Plural gate trenches are formed on an upper surface side of a semiconductor substrate of a first conductivity type. Gate electrodes are embedded in the plural gate trenches. Plural dummy gate trenches are formed at equivalent intervals between the neighboring gate trenches on the upper surface side of the semiconductor substrate. Dummy gate electrodes are embedded in the plural dummy gate trenches and connected with an emitter electrode. An interval between the gate trench and the dummy gate trench that neighbor each other is shorter than an interval between the neighboring dummy gate trenches.

The semiconductor device includes: a fourth impurity layer disposed in a state of being connected to the outermost peripheral second impurity layer and being separated from the first impurity layer between the outermost peripheral second impurity layer and the first impurity layer of the terminal portion, the fourth impurity layer having a second conductivity type and having an impurity concentration lower than an impurity concentration of the second impurity layer; an insulating film disposed on at least a part of the terminal portion, the insulating film having a first opening on the first impurity layer; and an electrode disposed on the insulating film, the electrode connected to the first impurity layer via the first opening.

A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 &#x3bc;m.

A semiconductor device includes gate trenches and dummy gate trenches formed on the upper surface side of a semiconductor substrate, gate electrodes embedded in the gate trenches, dummy gate electrodes embedded in the dummy gate trenches, a channel layer formed in the surface portion on the upper surface side of the semiconductor substrate, a carrier storage layer formed below the channel layer, and a collector layer formed on the lower surface side of the semiconductor substrate. A relationship D&#x3c;D&#x3c;D&#x3c;Dholds true, where Dis the depth of the bottoms of the gate electrodes, Dis the depth of the bottoms of the dummy gate electrodes, Dis the depth of the bottom of the carrier storage layer, and Dis the depth of the junction between the channel layer and the carrier storage layer.

Semiconductor device and power converter

A semiconductor device includes a well region, a buffer region, an insulating film, an electrode, and an electric field relaxing structure. An impurity concentration in the buffer region is reduced in a direction away from the active region. An end portion of the electrode is located at a position closer to the active region than an end portion of the buffer region. The electric field relaxing structure includes a plurality of RESURF layers each surrounding the buffer region in a plan view and formed in a surface layer of the semiconductor substrate.

A semiconductor substrate includes a first-conductivity drift layer, a first-conductivity first impurity layer, a second-conductivity base layer, and a first-conductivity first emitter region. The first impurity layer is provided on the drift layer, and has impurity concentration higher than impurity concentration of the drift layer. The base layer is provided on the first impurity layer. The first emitter region is provided on the base layer. The first impurity layer connects between trenches. The plurality of trenches are formed in the semiconductor substrate covered by a gate insulation film. The gate insulation film has a first thickness between a gate electrode and the drift layer in a side wall surface, and has a second thickness between the gate electrode and the drift layer in a bottom surface. The second thickness is larger than the first thickness.

A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P() to P() that decrease in this order, bottom-end distances D() to D() that increase in this order, and distances B() to B() to the edge of the semiconductor substrate that increase in this order. The surface concentration P() is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D() is in the range of 15 to 30 &#x3bc;m.

An insulated gate bipolar transistor having a gate electrode () and an emitter electrode () is provided in a transistor region. A termination region is arranged around the transistor region. A first N type buffer layer () is provided below an N type drift layer () in the transistor region. A P type collector layer () is provided below the first N type buffer layer (). A second N type buffer layer () is provided below the N type drift layer () in the termination region. A collector electrode () is directly connected to the P type collector layer () and the second N type buffer layer (). An impurity concentration of the second N type buffer layer () decreases as a distance from the collector electrode () decreases. The second N type buffer layer () does not form any ohmic contact with the collector electrode ().

A planar MOSFET is provided on the upper surface of the N-type semiconductor substrate in a mesa portion between the trenches. A P-type emitter layer is provided between the trench and the planar MOSFET in the mesa portion. A P-type collector layer is provided on a lower surface of the N-type semiconductor substrate. The planar MOSFET includes an N-type emitter layer, an upper portion of the N-type semiconductor substrate, a P-type base layer, and a planar gate on the foregoing with a gate insulating film interposed therebetween. The planar gate is connected to the gate trench. The P-type emitter layer has a higher impurity concentration than the P-type base layer and has an electric potential equal to an emitter potential of the N-type emitter layer. The N-type emitter layer is not in contact with the trench. A trench MOSFET is not formed.

An electric field buffer layer is formed so as to surround an active region. The electric field buffer layer includes a plurality of P-type impurity layers. Each of the P-type impurity layers includes P-type implantation layers and P-type diffusion layers that are formed so as to respectively surround the P-type implantation layers and contain P-type impurities at a concentration lower than that of the P-type implantation layers. A first P-type implantation layer is formed to be in contact with or to partially overlap the active region. Each of the P-type diffusion layers is formed to have an expansion to a degree to which the first P-type diffusion layer is in contact with or overlaps a second P-type diffusion layer. Intervals between the P-type implantation layers increase from the active region toward the outer peripheral portion of the semiconductor substrate.

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Tokyo, Japan

Ze Chen