Texas Instruments Corporation

Intersil Americas Inc.

Zbigniew Jan Lata

Ross Eliot Teggatz

David John Baldwin

Steven Patrick Laur

Alexander Noam Teutsch

Sanmukh Makan Patel

Jinyu Yang

Jingwei Xu

Bogdan M Duduman

William E Grose

Douglas M Mattingly

Jun Xu

A circuit and method for switching between a system's internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the system using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing.

Advanced clock synchronization circuit

In a switch mode power supply, a circuit and method for switching between an internal clock and an external synchronization clock when a stable external clock has been detected, and for switching back to operating the power supply using said internal clock when a predetermined number of sequential external clock pulses exceed a predetermined switching period dropout threshold or are otherwise missing. In one embodiment, a power system comprises a plurality of power supplies connected in parallel to a common load and where each power supply is synchronized to the external clock when a stable external clock has been detected by each.

Advanced clock synchronization circuit for switch mode power supplies

An IC incorporating a multiphase voltage converter with synchronized phase shift including a phase shift pin, a frequency select pin, a master clock pin, and a voltage regulator. The phase shift pin is coupled to a first voltage for a master mode or a first resistor for a slave mode. The frequency select pin is coupled to one of a second voltage and a second resistor. The master clock pin provides a master clock signal or receives an external clock signal. The IC provides the master clock signal at a frequency determined by the second resistor or otherwise at a default frequency. The voltage regulator operates in the slave mode at a phase shift relative to the external clock signal based on the first resistor and the second resistor or based on the first resistor and a default resistance if the second voltage is coupled.

Voltage regulator with synchronized phase shift

A system for controlling a plurality of load devices includes a high-side system operative to source current relative to at least two associated outputs. A low-side system is operative to sink current relative to a plurality of associated inputs. A control system controls the high-side system and the low-side system according to a multiplexing scheme that is operative to provide current to selected load devices of the plurality of load devices connected between the associated outputs and the associated inputs. The system can be implemented as an integrated circuit for driving the plurality of loads, which can include LED's.

System and method for driving a plurality of loads

System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch and filter block (SFB) (such as the SFB), a comparator (such as the comparator), and a fixed off time logic (FOTL) (such as the FOTL). The comparator compares an output voltage with a reference voltage. When the output voltage is equal to or exceeds the reference voltage, the comparator asserts a value on a signal line to the FOTL. The FOTL then shuts down the SFB for a specified period of time. During the off time, the output voltage decays. After the specified period of time expires, the SFB is turned back on and the output voltage can recharge. The duration of time that the SFB remains on is a function of the supply voltage, thus permitting an adjustable operating frequency.

Hysteretic controlled switch regulator with fixed off time

A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP for monitoring a phase of the switch mode circuit; a logic block having a first input coupled to a clock signal generator Oscillator, a second input coupled to an output of the hysteretic comparator HYST_COMP, and a third input coupled to an output of the standard comparator PHASE_COMP, wherein the logic block generates switching cycles based on a fixed ON/OFF time during a first part of a cycle and based on a hysteretic control during a second part of the cycle.

Switch mode regulator controller using hybrid technique

The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.

IC PMOS Schottky reverse bias protection structure

The present invention relates to a motor drive system which comprises a fan controller circuit operable to generate a PWM control signal for control of a motor speed. The fan controller circuit comprises a current detection circuit and a motor speed determination circuit. The system further comprises a fan driver circuit operable to drive a motor at a duty cycle based on the PWM control signal from the fan controller circuit. The fan driver circuit comprises a current sink circuit operable to draw current from the PWM control signal when the PWM control signal is high and when the motor reaches a predetermined position. In the addition, the current detection circuit is operable to detect the current draw on the PWM control signal and provide an indication signal to the fan speed determination circuit associated with such detection. Further, the motor speed determination circuit is operable to determine the speed of the motor based upon a timing associated with successive current draw detections. The present invention also relates to a method of determining a motor speed which comprises driving a motor at a duty cycle dictated by a PWM control signal and detecting a predetermined rotor position of the motor. The method further comprises generating a current pulse based on the rotor position, wherein the current pulse is convolved with the PWM control signal, detecting the current pulse, and determining the motor speed using successive detected current pulses.

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Plano, TX, United States of America

Zbigniew Jan Lata