Micron Technology Incorporated

Intel Corporation

Sony Semiconductor Solutions Corporation

Zailong Bian

Janos Fucsko

Hongqi Li

Jin Lu

Gowrisankar Damarla

Shyam Ramalingam

Thomas Gehrke

Roger W Lindsay

Yushi Hu

Eric Blomiley

Jaydip Guha

Jaydeb Goswami

Xiaolong Fang

Prasanna Srinivasan

John A Smythe

Michael P Violette

Muralikrishnan Balakrishnan

Xiaoyun Zhu

The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.

Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions

Electronic systems and methods of forming semiconductor constructions

A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.

Capping poly channel pillars in stacked circuits

Memory arrays

Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

Conductive structures, wordlines and transistors

A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via.

Integrated circuitry

Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments.

Method for forming a metal cap in a semiconductor memory device

Methods, devices, and systems associated with resistance variable memory device structures can include a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.

Confined resistance variable memory cells and methods

Methods, devices, and systems associated with resistance variable memory device structures are described herein. In one or more embodiments, a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode.

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Boise, ID, United States of America

Zailong Bian