Cloudshield Technologies, Inc.

Nvidia Corporation

Echelon Corporation

Cloudshield Teechnologies, Inc.

Zahid Najam

Peder J Jungck

Andrew Nguyen

Neil Hendin

Macduy T Vu

Ramachandra-Rao Penke

Jixue J Liu

Brian Lawrence Smith

Otto Steinbusch

Gregory Scott Triplett

Stephane Le Provost

Jose Alvarellos

Thuan Luong

An automatic load detection system. A first reference signal that may be known apriori can be used for load detection. For example, the first reference signal may be used for invisible portion of a frame. The DAC receives the first reference signal and outputs a signal that is based on the first reference signal. The output of the DAC may have two known values depending on whether the load is coupled to the DAC, e.g., by having a different impedance. Thus, the output signal may be used for detecting whether the load is uncoupled from the DAC. If it is determined that the load is uncoupled from the DAC, the clocking signal to the DAC may be turned off. Thus, DAC no longer consumes power when the load is uncoupled, thereby saving power.

Power management using automatic load/unload detection of DAC

A power management unit for improving power efficiency of an electronic device. The power management unit includes a first and a second stage power regulator and a control circuitry. The first stage power regulator includes a switching regulator to efficiently adjust an input voltage based on a feedback signal. The adjusted input voltage provides the second stage power regulator that includes low dropout voltage regulators with an input voltage close to its output. Thus, power dissipation in the second stage is reduced by reducing the voltage differential between the input and desired output voltages. The second stage turns on/off power to units of the electronic device. The control circuitry generates the feedback signal based on dropout voltages of the low dropout voltages, the desired output voltage and the adjusted input voltage. The largest dropout voltage is selected and adds it to the desired output voltage to generate the feedback signal.

Power management efficiency using DC-DC and linear regulators in conjunction

In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.

Integrated circuit device core power down independent of peripheral device operation

A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device. The shared memory may comprise a plurality of banks of synchronous dynamic random access memory (SDRAM) devices, and may be used to store packet data in a network.

Apparatus and method for interfacing with a high speed bi-directional network

An apparatus and method for interfacing a processor to one or more co-processors interface provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronously to the dual ported memory. Control logic monitors activity by the processor to alert the co-processors of communications by the processor written to the memory and otherwise allows the processor and co-processors to think they are interfacing directly with one another.

Apparatus and method for interconnecting a processor to co-processors using shared memory

An apparatus and method for interfacing a processor to one or more co-processors provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronously to the dual ported memory. Control logic monitors activity by the processor to alert the co-processors of communications by the processor written to the memory and otherwise allows the processor and co-processors to think they are interfacing directly with one another.

Apparatus and method for interconnecting a processor to co-processors using a shared memory as the communication interface

An architecture for intercepting and processing packets from a network is disclosed. The architecture provides both stateful and stateless processing of packets in the bi-directional network flow. Further, stateless processing is provided by a parallel arrangement of network processors while stateful processing is provided by a serial arrangement of network processors. The architecture permits leveraging existing bi-directional devices to process packets in a uni-directional flow, thereby increasing the throughput of the device. The ability to share state among the stateless processor, among the stateful processors of each packet flow direction and between the stateless and stateful processors provides for dynamic adaptability and analysis of both historical and bi-directional packet activity.

Edge adapter architecture apparatus and method

Apparatus and method for interfacing with a high speed bi-directional network using a shared memory to store packet data

An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the apparatus provides external connectivity to other devices that wish to intercept packets as well. The apparatus applies one or more rules to the intercepted packets which execute one or more functions on a dynamically specified portion of the packet and take one or more actions with the packets. The apparatus is capable of analyzing any portion of the packet including the header and payload. Actions include releasing the packet unmodified, deleting the packet, modifying the packet, logging/storing information about the packet or forwarding the packet to an external device for subsequent processing. Further, the rules may be dynamically modified by the external devices.

Edge adapter apparatus and method

A system and method for distributing power to multiple circuit boards coupled with a &ldquo;system&rdquo; backplane is disclosed. Separate redundant pairs of power supplies are provided for each circuit board in a load sharing arrangement. Each set of power supplies and their load, i.e. the circuit board to which they are coupled and providing power to, are isolated from the other sets. The power supplies are coupled with a second &ldquo;power&rdquo; backplane which interconnects the redundant power supply pairs as well as receives the input voltage and current from a source and distributes it to all of the power supplies. The power backplane is further coupled with the system backplane in a back to back arrangement to effect the connection of the power supplies with their respective loads. The redundant power supplies in combination with fault monitoring and failure handling logic identify and isolate faults, enable fail-over operation and prevent collateral damage to other system components.

Intelligent load sharing with power limiting scheme for multiple power supplies connected to a common load

System and method for distributed power supply supporting high currents with redundancy

A transmitting box is connected to a first electrical outlet in a building. The phase of the first electrical outlet is used as the reference phase. The transmitter box senses each of the zero-cross-overs of the reference phase and injects a data packet of the data carrier frequency at each zero-cross-over. A receiving box is connected to a second electrical outlet in the building. The second electrical outlet has an unknown phase which may be different from the reference phase. The receiver box receives each data packet and senses each phase zero-cross-over of the unknown phase. The receiver box uses the time between each reception of a data packet and each detection of an unknown phase zero-cross-over to determine the phase angle of the unknown phase relative to the reference phase.

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San Jose, CA, United States of America

Zahid Najam