Via Technologies, Inc.

Stmicroelectronics R&d Limited

Texas Instruments Corporation

Stmicroelectronics Gmbh

Zahid Hussain

John Wakefield Brothers

Huy Duc Bui

Jim Xu

Karl M Guttag

Wei Wang

Keith Balmer

David J Hoyle

Amarjit Singh Bhandal

Jiang-Ming Xu

Min-Jie Huang

Xin-Yang Yu

Kiumars Sabeti

The embodiments disclosed herein provide systems and methods for improved motion estimation using a graphics processing unit. One such embodiment includes a method for determining a motion vector describing motion relative to a reference block, which comprises determining which of a plurality of prediction blocks is a good match with the reference block, according to a match criteria. The method further comprises performing a local area exhaustive search, in an area centered around the good match prediction block, to produce a best match with the reference block. The best match has integral pixel resolution. The method further comprises modeling the degree of match between the best match and the reference block as a quadratic surface and analytically determining a minima of the quadratic surface, corresponding to a best matching block with fractional resolution. The method further comprises computing a fractional motion vector based on the best matching block with fractional resolution.

Systems and methods of improved motion estimation using a graphics processing unit

Included are embodiments for processing video data. At least one embodiment includes a logic configured to receive video data having a format chosen from at least two formats and logic configured to receive an instruction from an instruction set including an indication of the format of the video data. Some embodiments include first parallel logic configured to process video data according to a first format in response to the indication is the first format and second parallel logic configured to process the video data according to a second format in response to the indication is the second format.

VPU with programmable core

Methods and systems for performing control of flow in a graphics processor architecture are provided. For example, in at least one embodiment, a computing system includes a memory storing a plurality of instructions and a graphics processing unit. The graphics processing unit is configured to process the instructions according to a multi-stage scalar pipeline and store condition code values in the branch control stack. The graphics processing unit is further configured to process branch instructions using condition code values stored in the condition register at the top of the branch control stack.

Method and apparatus for performing control of flow in a graphics processor architecture

Included are embodiments for processing video data. At least one embodiment includes receive logic configured to receive the video data chosen from a plurality of formats and filter logic configured to filter the video data according to the instruction. Similarly, some embodiments include transform logic configured to transform the video data according to the instruction, where the instruction contains a mode indication in which the filter logic and the transform logic execute based on the format of the video data.

Filtering for VPU

An exemplary video decoder comprises: an entropy decoder; a spatial decoder; combining logic; and an inloop deblocking filter. The entropy decoder receives an incoming coded bit stream. The spatial decoder receives the output of the entropy encoder and produces an encoded picture comprising a plurality of pixels. The combining logic combines a current picture with a prediction picture to produce a combined picture. The inloop deblocking filter receives the combined picture. The inloop deblocking filter comprises: logic configured to filter a predefined pixel group; and logic configured to filter each of the remaining pixel groups in the plurality after the predefined pixel group, according to a corresponding set of taps in a plurality of sets of taps, if the predefined pixel group meets a criteria.

Systems and methods of video compression deblocking

An intra-frame prediction method and a prediction apparatus using the same are provided. The prediction apparatus includes an input data unit, a control unit, an selection unit, a processing unit, and an output data selecting unit. The input data unit provides surroundings pixels of a predicted block. The control unit provides an input selection signal, a computing parameter, and an output selection signal. The selection unit selects the surroundings pixels according to the input selection signal. The processing unit computes the selected surroundings pixels for producing a plurality of results according to the computing signal. The output data unit selects results according to the output selection signal.

Intra-frame prediction method and prediction apparatus using the same

Disclosed is a graphics processing unit comprising an instruction decoder and sum-of-absolute-differences (SAD) accleration logic. The instruction decoder is configured to decode a SAD instruction into parameters describing an M&#xd7;N and an n&#xd7;n pixel block in U,V coordinates. The SAD accleration logic is configured to receive the parameters and compute SAD scores. Each SAD score corresponds to the n&#xd7;n block and to one block contained within the M&#xd7;N pixel block and horizontally offset within the n&#xd7;n block. Also disclosed is a GPU comprising a host processor interface receiving video acceleration instructions and a video acceleration unit. The unit is responsive to the instructions and comprises SAD accleration logic configured to receive the parameters and compute SAD scores. Each SAD score corresponds to an n&#xd7;n pixel block and to one block contained within an M&#xd7;N block and horizontally offset within the n&#xd7;n block. M, N, and n are integers.

An exemplary graphics processing unit (GPU) comprises a decoder and a video processing unit. The decoder is configured to decode a first and a second deblocking filter acceleration instruction. The first and second deblocking filter instructions are associated with a deblocking filter used by a particular video decoder. The video processing unit is configured to receive encoded by the deblocking filter acceleration instructions, and to determine first and second memory sources specified by the received parameters as one of a plurality of memory sources located on the GPU. The video processing unit is further configured to load a first block of pixel data from the first memory source, and to apply the deblocking filter to the first block of pixel data, and to load a second block of pixel data from the second memory source, and to apply the deblocking filter to the second block of pixel data.

Embodiments of exponent processing systems and methods are disclosed. One method embodiment, among others, comprises performing a first table lookup using a first address to provide a first value corresponding to the first component part, setting an integer exponent to provide an integer-based value corresponding to the integer component, performing a second table lookup using a second and third address to provide a second value and a third value corresponding to the second component part and the third component part, respectively, expanding and normalizing the second and third values to provide expanded and normalized second and third values, combining the expanded and normalized second and third values to produce a first product, and computing the exponential function by combining the first value, the integer-based value, and the first product.

Exponent processing systems and methods

A processor and a method for executing VLIW instructions by first fetching a VLIW instruction and then identifying from option bits encoded in a first one of the instructions within the fetched VLIW instruction packet which, if any, of the remaining instructions within the VLIW instruction are to be executed in the same execution cycle as the first instruction. Finally, executing the first instruction and any remaining instructions identified from the encoded option bits.

Processor instruction including option bits encoding which instructions of an instruction packet to execute

A processor and a method for executing VLIW instructions using pipeline execution wherein each VLIW instruction includes a plurality of instructions and wherein the pipeline includes at least the following stages: first and second instruction fetch stages, a pre-decode stage, an instruction dispatch stage, first and second decoding stages, an execution stage and a write-back stage. During the first instruction fetch stage the number of outstanding instructions is determined where these outstanding instructions are from previous VLIW instructions that have not yet been issued for execution. During the second instruction fetch stage a comparison is performed on whether the number of outstanding instructions is less then the number of instructions in a VLIW instruction where if the number of outstanding instructions is less than the number of instructions in an instruction packet then the next VLIW instruction is fetched and the outstanding instructions are shifted and aligned with the fetched VLIW instruction. During the pre-decode stage determining which instructions in each VLIW instruction are to be issued and in the dispatch stage feeding the instructions not issued back to the first instruction fetch stage such that the processor is updated as to the number of outstanding instructions.

Pipelined processing using option bits encoded in an instruction

Embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a context-adaptive binary arithmetic (CABAC) unit configured to execute a shader, the shader configured to implement CABAC decoding of a video stream and provide a decoded data output.

Decoding of context adaptive binary arithmetic codes in computational core of programmable graphics processing unit

Various embodiments of decoding systems and methods are disclosed. One method embodiment, among others, comprises providing a shader configurable with a plurality of instruction sets to decode a video stream coded a plurality of different coding methods, loading the shader having one of the plurality of instruction sets to a variable length decoding (VLD) unit of a software programmable core processing unit for execution thereof, and decoding the video stream by executing the shader on the VLD unit.

Decoding control of computational core of programmable graphics processing unit

Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a variable length decoding unit (VLD) unit configured to execute a shader, the shader configured to selectively implement decoding of a video stream coded based on a plurality of different coding methods to provide a decoded data output, wherein the decoding is implemented using a combination of software and hardware.

Decoding systems and methods in computational core of programmable graphics processing unit

Various embodiments of decoding systems and methods are disclosed. One system embodiment, among others, comprises a software programmable core processing unit having a context-adaptive variable length coding (CAVLC) unit configured to execute a shader, the shader configured to implement CAVLC decoding of a video stream and provide a decoded data output.

Growing community of inventors

Ascot, United Kingdom

Zahid Hussain