Marvell Asia Pte., Ltd.

Transwitch Corporation

Advanced Micro Devices Corporation

Zahi S Abuhamdeh

Vincent D'Alessandro

Thucydides Xanthopoulos

Nitin Mohan

Michael Ricchetti

Samuel Rodriguez

Kandadi Vasudevan

Richard Lombard

Tyler Albarran

Arun Hegde

Shunquan Shen

Peter Rickenbach

Clock distribution circuitry, for distributing clocks for scan operations in an integrated circuit device in which a mission mode clock is distributed by a mesh clock structure and a scan fabric clock is distributed by a scan clock bus, includes a mesh clock source, and a local distribution structure for distributing the clocks for scan operations to a local clock domain that includes a subset of taps of the mesh clock structure. The local distribution structure includes a local controller for controlling derivation of a scan capture clock from the mesh clock source, local scan host circuitry for deriving a local scan shift clock from the scan fabric clock, and specialized integrated clock gates corresponding in number to the subset of taps of the mesh clock structure, for selecting between the scan capture clock in a scan capture mode, and the local scan shift clock in a scan shift mode.

Clock gating for scan shift clock in a mesh clock environment

A system for performing a failure assessment of an IC may comprise a hardware subsystem and a control subsystem to control operations performed by the hardware subsystem. The hardware system may change a duration of cycles of a clocking signal on the IC, and stop the clocking signal at a selected clock cycle. The operations may comprise changing the duration of selected clock cycles across a block of clock cycles, and performing a binary search across the block of clock cycles, such that the selected clock cycles are temporally placed at selected different locations within the block of clock cycles. At each iteration of the binary search, the system determines when a failure occurs. When the binary search indicates a single clock cycle causing a failure, the system stops clocking transitions at the single clock cycle, and the system extracts data from one or more circuit components of the IC.

System and method for performing a failure assessment of an integrated circuit

A system may measure a first sample, of a first signal, using an undersampling signal. The system may measure a second sample, of a second signal, using the undersampling signal. The undersampling signal may have a frequency that is based on a frequency of the first signal or a frequency of the second signal. The system may detect, based on measuring the first sample, a first edge of the first signal. The system may detect, based on measuring the second sample, a second edge of the second signal. The system may determine a delay, associated with the first signal and the second signal, based on detecting the first edge, based on detecting the second edge, based on a first cycle time of the undersampling signal, and based on a second cycle time of the first signal or the second signal.

Measuring delay between signal edges of different signals using an undersampling clock

According to the methods of the invention, a further delayed DLL signal is compared to the reference clock and a delayed reference clock signal is compared to a DLL signal. These two comparisons are performed on the 360&#xb0; signal and on the 180&#xb0; signal. The delay introduced by the methods of the invention is preferably adjustable based on the results of a process monitor test. The process monitor test can be run continuously and accounts for process, voltage and temperature. The methods of the invention can also be used to test for clock skew in a clock tree on a chip.

Methods and apparatus for testing delay locked loops and clock skew

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Billerica, MA, United States of America

Zahi S Abuhamdeh