Intel Corporation

Marvell International Limited

Zafer Kadi

Addicam V Sanjay

Jose A Avalos

Eric R Auzas

Murthi Nanja

Rajnish Maini

Highland Mary Mountain

Zana Ilhan

Systems and methods for displaying content from a multi-use fog device are provided. The multi-use fog device may include a processor to execute code segments, and a floating-point gate array (FPGA) card that is coupled to the processor through a PCIe interface. The FPGA card includes a header for connecting sensors to the multi-use fog device, and an FPGA that provides video processing for the multi-use fog device.

Multi-use fog device

A biometric keyboard or other input device, such as a keypad or touch screen, may be part of an input mechanism for inputting user information to a computing system. The mechanism may include biometric sensors associated with the buttons or keys of the input device. A mapping scheme may be used such that the input value forwarded to a processing resource when a user activates one or more of the buttons or keys varies depending on which digit (finger, toe, etc.) was used to activate the key(s) or button(s). Other embodiments are also described and claimed.

Bio-metric input mechanism

A method for off loading resource intensive compilations is disclosed. The method may include enabling a user of a wireless handheld device to request a platform independent application. The wireless handheld device may be enabled to assess a resource on the wireless handheld device and to determine whether to request native code for the platform independent application. The method may also include enabling the requested platform independent application to be routed to a trusted server. The trusted server may compile the platform independent application into native code for the wireless handheld device and may transport the native code to the wireless handheld device for execution.

End-to-end architecture for mobile client JIT processing on network infrastructure trusted servers

A processor-based device (e.g., a wireless device) may include a processor and a semiconductor memory (e.g., a flash memory) to selectively pipeline and prefetch memory data, such as executable data, in one embodiment, using prefetch/pipeline logic that may enable storage of a first indication associated with executable data at a first storage location and a second indication associated with executable data at a second storage location. Upon retrieval, the prefetch/pipeline logic may selectively perform at least one of pipelining and prefetching of the executable data associated with the second storage location based on the first indication.

Growing community of inventors

Tempe, AZ, United States of America

Zafer Kadi