Intel Corporation

Zack Waters

Travis T Schluessler

Michael Apodaca

Jason M Surprise

Murali Ramadoss

Ankur N Shah

Peter L Doyle

Prasoonkumar Surti

Subramaniam M Maiyuran

Saurabh Sharma

Daniel D Johnston

Ravishankar Iyer

Carl S Marshall

Selvakumar Panneer

Mrutunjayya Mrutunjayya

Charles Moidel

Jacob N Smith

Slawomir Grajewski

Mike Apodaca

An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.

Inferred shading mechanism

Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

Multi-tile memory management mechanism

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

Position-based rendering apparatus and method for multi-die/GPU graphics processing

Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.

High-speed resume for GPU applications

Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.

High vertex count geometry work distribution for multi-tile GPUs

Apparatus and method for resilient interface for updating a graphics processor. For example, one embodiment of an apparatus comprises a graphics processor; and a configuration memory of the graphics processor to be subdivided into a plurality of configuration regions associated with a corresponding plurality of graphics pipeline stages and/or functional units, wherein a host processor executing a graphics driver is to submit a graphics processor configuration update to a command buffer, the graphics processor configuration update including at least one logical memory address associated with a logical view of the configuration memory and configuration data to be used to modify at least one configuration region associated with the at least one logical memory address, and wherein the logical memory address is to be used to identify a corresponding physical memory address for at least one configuration region corresponding to at least one of the graphics pipeline stages and/or functional units, the at least one configuration region to be responsively updated.

Interface apparatus and method resilient to graphics hardware changes

Methods, apparatus and articles of manufacture for graphics processing of a vertex buffer using a relative index buffer are disclosed. Example methods to process a vertex buffer disclosed herein include accessing a first relative index stored in a relative index buffer, the first relative index specifying an offset from a current index selecting a first entry of the vertex buffer. Such disclosed example methods also include, in response to the first relative index being a nonzero value, processing data associated with a second entry of the vertex buffer to determine a rasterizer output associated with the first entry of the vertex buffer, the second entry of the vertex buffer being selected using the current index offset by the first relative index.

Graphics processing of a vertex buffer using a relative index buffer

Methods and apparatus relating to sort-free threading model for a multi-threaded graphics pipeline are described. In an embodiment, draw requests, corresponding to one or more primitives in an image, are stored in entries of a queue (e.g., in the order received). Each entry remains locked until both a front-end and a back-end of a graphics pipeline have completed one or more operations associated with the draw request. Other embodiments are also disclosed and claimed.

Growing community of inventors

Portland, OR, United States of America

Zack Waters