Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Zachy Haramaty

Aviv Kfir

Barak Gafni

Eitan Zahavi

Benny Koren

Liron Mula

Itamar Rabenstein

Amiad Marelli

Freddy Gabbay

Ido Bukspan

Gil Levy

Diego Crupnicoff

George Elias

Ran Ravid

Gil Bloch

Matty Kadosh

Oded Wertheim

Alon Singer

Lion Levi

Roy Kriss

Oded Zemer

Ilya Vershkov

Noam Katz Abramovich

Shachar Bar Tikva

Ran Shani

Maty Golovaty

Dekel Dadon

Idan Burstein

Ariel Almog

Miriam Menes

Alon Webman

Andrey Ger

Vladimir Zdornov

Alex Shpiner

Aviad Raveh

Yaniv Strassberg

Tamir Ronen

Idan Matari

Aviv Barnea

Nir Monovich

Jacob Ruthstein

Shachar Dor

Shy Zimmerman

Itsik Levi

Aviv Hasson

Gal Shohet

Elan Rohekar

Tom Munk

Zvika Eyal

Michael Taher

Oded Nadir

Eduard Kvetny

Barry Spinney

Amit Solomon

Shahar Givony

Yehezkel Rothbaum

A device includes multiple registers, multiple hardware-implemented Privilege Level Indicators (PLIs), and one or more circuits. The registers are to store respective values. The PLIs are to specify privilege levels for accessing the respective registers. The one or more circuits are to perform a secure memory dump operation including (i) checking the PLIs of one or more of the registers and (ii) outputting the values of the registers that are permitted for outputting according to the respective PLIs.

Integrated-circuit memory dump using hardware security mechanism

A system includes a communication bus, a controller device, and a target device. The controller device and the target device may transition between different communication protocols in association with transferring data over the communication bus. The target device may receive a transaction command including a slave address. Based on the slave address, the target device may determine a communication protocol associated with transferring data in association with the transaction command. A first communication protocol may include a message protocol, and the message protocol may be associated with an I2C communication protocol or an I3C communication protocol. The second communication protocol may include a bus protocol, and the bus protocol may be associated with the I2C communication protocol.

Hot transition of I2C to I3C

A network adapter includes a port and one or more circuits. The port is to send packets to a network in accordance with a Remote Direct Memory Access over Converged Ethernet (RoCE) protocol. The one or more circuits are to decide whether a packet is permitted to undergo Adaptive Routing (AR) in being routed through the network, to mark the packet with an indication of whether the packet is permitted to undergo AR, and to send the marked packet to the network via the port.

Marking of RDMA-over-converged-ethernet (RoCE) traffic eligible for adaptive routing

A relay device is provided that may identify a quantity of empty data byte locations in a data buffer of the relay device. The relay device may receive an indicator associated with transmitting data packets. The relay device may pause or enable a lossless flow of data between the relay device, a host device, and a peer device based on the quantity of empty data byte locations, the indicator, or both. The relay device may include a first data interface coupled with a peer device, a second data interface coupled with a host device, a data buffer configured to store data packets received from the host device, and a state machine that enables a lossless transmission of data between the host device and peer device. The state machine may transmit a pause frame to the host device based on a data buffer utilization reaching a data storage capacity.

Ethernet pause aggregation for a relay device

An apparatus includes an input interface to receive incoming packets from a first network device and an output interface to send outgoing packets to a second network device. Media access control security (MACsec) circuitry is coupled between the input interface and the output interface. Bypass flow-control (FC) circuitry is coupled between the input interface and the MACsec circuitry. The bypass FC circuitry is to detect an FC packet in the incoming packets and pass the FC packet passively to the output interface to enable end-to-end flow control directly between the first network device and the second network device.

End-to-end flow control with intermediate media access control security devices

A device including a cable transceiver including cable electrical connections including data electrical connections and control electrical connections, and a hardware memory device, the hardware memory device storing a string identifying a cable and being electrically accessible from externally to the cable transceiver via the control electrical connections. The cable, in electrical connection with the cable electrical connections, may be included in the device. A device for verifying cable authenticity is also described, the device including interface hardware for interfacing a plurality of cables with the device, and verifier circuitry configured to verify that each of the plurality of cables is genuine based on a string stored in a hardware memory device included in each of the plurality of cables. Related apparatus and methods are also described.

Cable security

A System-On-Chip (SoC) includes a set of registers, a processor, and Out-Of-Order Write (OOOW) circuitry. The processor is to execute instructions including write instructions. After issuing a first write instruction to any of the registers in the set, the processor is to await an acknowledgement for the first write instruction before issuing a second write instruction to any of the registers in the set. The OOOW circuitry is to identify the write instructions issued by the processor to the registers in the set, to perform the identified write instructions in the registers irrespective of acknowledgements from the registers, and to send to the processor imitated acknowledgements for the identified write instructions.

Out-of-order input / output write

An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

Processor with split read

A networking system includes a pluggable security device comprising at least one port interface that is insertable into at least one physical port, memory that stores a security key used to provide security over a network link, and processing circuitry coupled with the at least one port interface and with the memory. The processing circuitry utilizes the security key to verify security of a point-to-point connection established over the network link and after verifying the security of the point-to-point connection, provides a data integrity check function for data packets received at the at least one port interface.

Pluggable security devices and systems including the same

One embodiment includes a network device including multiple interfaces to serve as ingress ports for receiving network packets from nodes in remote customer-site network(s) via a tunnel in a provider network, and from nodes in a local customer-site network, and egress ports for forwarding at least some of the network packets, and control circuitry to make a decision to drop a network packet to reduce packet duplication in at least one of the nodes, responsively to the network packet being identified as a packet of broadcast, unknown unicast, or multicast traffic, the network packet being subject to decapsulation of an encapsulation header, being assigned to one of the egress ports, and having a header including one of a plurality of virtual local area network identifications, or one of a plurality of source identifications.

Scalable pipeline for EVPN multi-homing

In one embodiment a network device includes multiple interfaces including at least one egress interface, which is configured to transmit packets belonging to multiple flows to a packet data network, control circuitry configured to generate event-reporting data-items, each including flow and event-type information about a packet-related event occurring in the network device, a memory, and aggregation circuitry configured to aggregate data of at least some of the event-reporting data-items into aggregated-event-reporting data-items aggregated according to the flow and event-type information of the at least some event-reporting data-items, store the aggregated-event-reporting data-items in the memory, and forward one aggregated-event-reporting data-item of the aggregated-event-reporting data-items to a collector node, and purge the one aggregated-event-reporting data-item from the memory.

Telemetry event aggregation

A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

Hardware acceleration for uploading/downloading databases

A method including altering the configuration of a system including a processor, firmware storage and a scratchpad from a first configuration in which a first version of firmware enabling a first plurality of system operations is run by the processor, into a second configuration in which a second version of firmware enabling a second plurality of system operations is run by the processor, the altering including: A) re-configuring the system from the first configuration into an intermediate configuration in which the processor continues to run the first version of the firmware, B) while the system is in the intermediate configuration, disallowing at least one of the first plurality of operations, C) re-configuring the system from the intermediate configuration to the second configuration, and D) while the system is in the second configuration, allowing the second plurality of operations. Related apparatus and methods are also provided.

In-service software/firmware update

A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.

Simplified packet routing

Growing community of inventors

Hemed, Israel

Zachy Haramaty