Hewlett-packard Development Company, L.P.

Zachary Steven Smith

John Warren Maly

Ryan Clarence Thompson

Adam Caison Brown

David Heckman

Lee Becker

Ryan Clarenc Thompson

A method and apparatus for tracking packets in a processor architecture verification system are disclosed herein. An embodiment of the method comprises identifying a completion event associated with the transfer of a packet across a point to point link network of a virtual bus interface; creating an identification for the packet; and storing data associated with the packet in a database, the data being indexable by way of the identification.

Processor architecture verification

A computer implemented method of verifying events generated by an agent includes detecting an input signal at an input of the agent, generating an expected output signal based at least in part on the input signal, detecting an output signal at an output of the agent, wherein the output signal is a translation of the input signal generated by the agent, and comparing the output signal with the expected output signal to verify whether the agent produced the output signal correctly based on the input signal.

Expectation based event verification

A computer implemented method of verifying events generated by an agent includes detecting a stimulus at an input of the agent and determining whether generation of an event by the agent in response to the stimulus is conditional. An expectation of the event is created based at least in part on the stimulus, wherein the agent is expected to generate the event. The method also includes making the expectation speculative if the generation of the event is conditional.

Speculative expectation based event verification

In one embodiment, a system and method for identifying incomplete transactions includes identifying termination of a test case run on a processor verification system, examining a pending transaction list to identify incomplete transactions, and examining at least one forward progress vector to identify incomplete transactions.

Systems and methods for identifying incomplete transactions

Disclosed are systems and methods for identifying erroneous transactions. In one embodiment, a system and a method pertain to monitoring an interface, determining information related to termination of a test case, and after the test case has terminated, identifying an incomplete transaction that should have completed prior to termination of the test case.

Systems and methods for identifying erroneous transactions

In one embodiment, a system and method pertain to identifying an output signal having indeterminate timing, creating an expectation for a signal change associated with the output signal, and adding the expectation to an ordered list of expectations for the output signal. In another embodiment, a system and method pertain to detecting a signal change, identifying a vector associated with the signal in which the change occurred, examining pending expectations of the vector until a mature expectation is identified, comparing an expected value contained in the mature expectation with the detected signal change, and reporting an error if the expected value does not match the detected signal change.

Systems and methods for conducting future signal checks

A method and apparatus for ordering test cases for regression testing in a regression test system. The regression testing may include executing ordered test cases identified and ordered according to preferences. Each prospective test case may be assigned a result record for retaining previous testing history of the specific test case as well as the design model tested. The test may be selected according to preferences that yield more timely discovery of design bugs. Once ordered, the ordered test cases may be tested against a current design model, which results in test results, at least a portion of which updates the corresponding result record.

Method and apparatus for ordering test cases for regression testing

Systems, methodologies, media, and other embodiments associated with a system for producing a bus-type header-type field from a point-to-point data-type field are described. One exemplary system embodiment includes a logic configured to identify that a point-to-point transaction includes non-memory-data information encoded in a data flit, a logic configured to extract the non-memory-data information from the data flit, and a logic configured to produce a header-type field for a bus-type transaction produced by the virtual bus interface from the point-to-point transaction.

Virtual bus interface production of header-type fields from data-type fields

Systems, methods and software products are provided for transaction logging and intelligent error reporting in an expectation-based memory agent checker. Simulation status information is appended to one or more transaction log messages generated by the expectation-based memory agent checker. A cause of error indicated by mismatch between simulated output transaction events and expected output transaction events is determined. Information about the error is appended to one or more error messages generated by the expectation-based memory agent checker.

Transaction logging and intelligent error reporting in an expectation-based memory agent checker

Techniques are disclosed for automatically generating test instructions for use in testing a microprocessor design. A configuration file includes a plurality of knobs which specify a probability distribution of a plurality of microprocessor instructions. A random code generator takes the configuration file as an input and generates test instructions which are distributed according to the probability distribution specified by the knobs. The test instructions are executed on the microprocessor design. The microprocessor behaviors that are exercised by the test instructions are measured and a fitness value is assigned to the configuration file using a fitness function. The configuration file and its fitness value are added to a pool of configuration files. A configuration file synthesizer uses a genetic algorithm to synthesize a new configuration file from the pool of existing configuration files. This process may be repeated to generate configuration files which increasingly exercise microprocessor behaviors which are of interest.

Growing community of inventors

Fort Collins, CO, United States of America

Zachary Steven Smith