General Electric Company

Cornell University

Zachary Matthew Stum

Stephen Daley Arthur

Kevin Sean Matocha

Peter Almern Losee

Jesse Berkley Tucker

Richard J Saia

Ljubisa Dragoljub Stevanovic

Vinayak Tilak

Reza Ghandi

Emad Andarawis Andarawis

Thomas Bert Gorczyca

Jody Alan Fronheiser

Peter Micah Sandvik

Robert E Thorne

Jan Kmetko

Dale M Brown

Alexander Viktorovich Bolotnikov

Ahmed Elasser

Richard Alfred Beaupre

James Jay McMahon

Stanislav Ivanovich Soloviev

Gregory Keith Dudoff

Kevin O'Neill

Larry Burton Rowland

Cheng-Po Chen

Kuna Venkat Satya Rama Kishore

James William Kretchmer

Ramakrishna Rao

William Gregg Hawkins

Roger Raymond Kovalec

Greg Thomas Dunne

Peter Almren Losee

Richard Joseph Saia

Kuna Venkat Kishore

James Mcmahon

James Jay Mcmahon

The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.

Tapered gate electrode for semiconductor devices

A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.

Systems and method for ohmic contacts in silicon carbide devices

A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0&#xd7;10per cm.

Semiconductor device with junction termination extension

Systems and methods for ohmic contacts in silicon carbide devices

An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.

Systems and methods for terminating junctions in wide bandgap semiconductor devices

A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.

Semiconductor device and method of manufacturing the same

A method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands.

Integrated circuit and method of fabricating same

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

Silicon-carbide MOSFET cell structure and method for forming same

The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800&#xb0; C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 &#x3bc;m. A vertical SiC MOSFET is also provided.

SiC MOSFETs and self-aligned fabrication methods thereof

In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well () (P type) and two parallel sources () (N type) formed within the well. A plurality of source rungs () (doped N) connect sources () at multiple locations. Regions between two rungs () comprise a body () (P type). These features are formed on an N-type epitaxial layer (), which is formed on an N-type substrate (). A contact () extends across and contacts a plurality of source rungs () and bodies (). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.

A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.

MOSFET devices and methods of making

A method for doping impurities into a device layer includes providing a carbonized dopant layer including one or more dopant impurities over a device layer and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device layer.

Method for doping impurities

A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.

Silicon carbide devices and method of making

A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.

Method for fabricating silicon carbide vertical MOSFET devices

A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.

Growing community of inventors

Niskayuna, NY, United States of America

Zachary Matthew Stum