Hyperchip Inc.

Cadeka Microcircuits, LLC

Other

Technologies Ltrim Inc.

Nortel Networks Corporation

Polyvalor S.e.c.

Ecole De Technologie Superieure Polyvalor, Limited Partnership

Ltrim Technologies Inc.

Yvon Savaria

Yves Gagnon

Alain Lacourse

Michel Meunier

Claude Thibeault

Hugo St-Jean

Mathieu Ducharme

Yves Blaquiere

Meng Lu

Jean-Jacques Laurin

Zhong-Fang Jin

Hugues Langlois

Richard S Norman

François Gagnon

Mohamad Sawan

Jean-François Harvey

Philippe Dumais

Martin Roy

Jonathan Coulombe

Mohamed Lassaad Ammari

Colince Donfack

Karl Fecteau

Nanhan Xiong

Bernard Antaki

Sarnan M Adham

Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source.

Tunable semiconductor component provided with a current barrier

A method and apparatus is disclosed for performing a multi-equalization of a transmitted signal on a channel having varying characteristics comprising equalizing the transmitted signal using a plurality of setting defining a plurality of equalizing functions to provide a corresponding plurality of symbol signal, synchronizing each of the plurality of symbol signals to provide a plurality of synchronized signals, selecting at least one of the plurality of synchronized signals according to at least one transmission performance criterion and providing the selected one of the plurality of synchronized signals.

Multi-equalization method and apparatus

In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Methods, apparatus, and systems for reducing interference on nearby conductors

A communications bus enables communication of data signals in a parallel processing system having a plurality of substantially identical cells, each cell having an access point for transmitting data signals into the communications bus. The communications bus includes a plurality of parallel channels, and at least one channel crossover point associated with each cell. Each crossover point implements a regular change in a channel order of the communications bus, such that each access point is coupled to a channel of the communications bus. Propagation delays are reduced by inserting buffers at regular intervals along the length of each channel. An output buffer at a downstream boundary of each power domain of the system prevents undesired currents due to voltage mismatch. The propagation direction of data signals away from the access point, and propagation of data to an adjacent downstream cell can be controlled to reduce bus traffic and power consumption.

Communications bus for a parallel processing system

A method is provided for tuning (i.e. modifying, changing) the impedance of semiconductor components or devices using a focused heating source. The method may be exploited for finely tuning the impedance of semiconductor components or devices, by modifying the dopant profile of a region of low dopant concentration (i.e. increasing the dopant concentration) by diffusion of dopants from adjacent regions of higher dopant concentration through the melting action of a focused heating source, for example a laser. The present invention is in particular directed to the use of lasers in relation to circuits for the creation of conductive links and pathways where none existed before. The present invention more particularly relates to a means wherein impedance modification (i.e. trimming or tuning) may advantageously be carried out as a function of the location of one or more conductive bridge(s) along the length of a gap region.

Method for modifying the impedance of semiconductor devices using a focused heating source

A miniaturized body electronic implant for providing artificial vision to a blind person or for other uses as neuro-muscular sensors and microstimulators. The implant has a high resolution electrode array connected to a chip integrating implant stimulation and monitoring circuits, mounted on the back of the electrode array. The implant is powered by and communicates with an external unit through an inductive bi-directional link.

Body electronic implant and artificial vision system thereof

A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing system. For each IC under test, a set of redundant TAPs perform a boundary scan, and the test results are combined by voting. The TAPs of each set are physically diverse, in that they are physically located in separate power domains of the parallel processing system. As a result, the scan chain is robust to faults affecting power and/or control signal supply to any one power domain. Respective input and output dummy cells at opposite extreme ends of the scan chain provide a graceful separation and recombination of the redundant parallel scan chains, and so renders the architecture of the scan chain transparent to external boundary scan circuit elements.

Fault tolerant scan chain for a parallel processing system

In a method of data transmission according to one embodiment of the invention, data transitions having the same clock dependence are separated in space. In one such method, signals of one set are transmitted on corresponding conductive paths in one direction, signals of another set are transmitted on corresponding conductive paths in the other direction, and adjacent conductive paths that each carry a signal of one set are separated by at least one conductive path that carries a signal of another set. In an apparatus according to one embodiment of the invention, the conductive paths are fabricated on a semiconductor substrate.

A reticle and method simultaneously generate small- and large-scale circuit structures of a parallel processing system. The reticle includes at least two circuit traces having respective contact pads within an overlap zone of the reticle. Connectivity between a circuit trace of one reticle image with a circuit trace of an adjacent reticle image is controlled by varying the degree of overlap between the two images.

Method of generating large scale signal paths in a parallel processing system

In a method of data transmission according to one embodiment of the invention, signals on adjacent conductive paths pass through different sequences of inversions and regenerations. In an apparatus according to one embodiment of the invention, two sets of parallel transmission lines include series of inverting and non-inverting buffers having different sequences.

The invention relates to a method of iteratively, selectively tuning the impedance of integrated semiconductor devices, by modifying the dopant profile of a region of low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of higher dopant concentration through the melting action of a focussed heating source, for example a laser. In particular the method is directed to increasing the dopant concentration of the region of lower dopant concentration, but may also be adapted to decrease the dopant concentration of the region.

Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source

It is common that the presence of a defect causes abnormal gate output voltage excursions in data buffers, AND gates, OR gates and multiplexers in current-mode logic circuits. A voltage excursion is detected by a voltage excursion detection apparatus which includes a built-in detector. The detector, which is little overhead, is used to monitor output swings of all gates (differential circuits) and flags all abnormal voltage excursions. These detection results cover classes of faults that cannot be tested by stuck-at testing methods only. The voltage detection apparatus works well below 'at-speed' frequencies.

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Montreal, Canada

Yvon Savaria