Bull Cp8

Yvon Gressus

Michel Ugon

Christoph Siegelin

The present invention relates to a smart integrated circuit. This smart integrated circuit is characterized in that it has a main processor () and an operating system executing a main program (P) for constituting a main task-performing process, at least one secondary processor () capable of concurrently executing at least one secondary program (P) for constituting at least one task-performing process, power supply circuits () common to the processors and means for ensuring that the secondary processor or processors with similar power and different operating signatures are executed concurrently with the main process by continuously or intermittently inducing, in the power supply circuits, power disturbances that are superimposed on those of the main process so as to produce a continuous or intermittent scrambling.

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Les Clayes Sous Bois, France

Yvon Gressus