Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Stmicroelectronics S.a.

Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique

Other

Stmicroelectronics Gmbh

Stmicroelectronics (grenoble 2) Sas

Stmicroelectronics (rousset) Sas

Yves Morand

Maud Vinet

Laurent Grenouillet

Heimanu Niebojewski

Fabrice Nemouchi

Cyrille Le Royer

Thierry Poiroux

Shay Reboh

Louis Hutin

Laurent Clavelier

Yves Campidelli

Sylvain Maitrejean

Jean-Charles Barbe

Jean-Francois Damlencourt

Olivier Kermarrec

Nicolas Posseme

Daniel Bensahel

Emmanuel Augendre

Romain Wacquez

Yannick Le Tiec

Sylvain Barraud

Julien Borrel

Daniel-Camille Bensahel

Sébastien Barnola

Vincent Cosnier

Olivier Demolliens

Philippe Coronel

Hubert Moriceau

Thomas Skotnicki

Charles Baudot

Frédéric Boeuf

Perrine Batude

Aomar Halimaoui

Frédéric Gaillard

Frederic-Xavier Gaillard

Jean-Luc Pelloie

Mehdi Moussavi

Benoit Mathieu

Francois Rieutord

Jean-Pierre Colinge

François Rieutord

Denis Mariolle

Benjamin Vincent

Robin Cerutti

Jean-François Damlencourt

Stéfan Landis

Yorick Trouiller

Yveline Gobil

Maxime Garcia-Barros

Frédéric Milesi

David Fraboulet

Sébastien Desplobain

Benoit Vianay

Pascale Berruyer

Fran&ccedil;oise Vinet

Myriam Assous

Maxime Moulin

Mikael Casse

Method for making a transistor, comprising:

Method for making a transistor of which the active region includes a semimetal material

There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

Fabrication of transistors having stressed channels

There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600&#xb0; C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.

Method for producing low-permittivity spacers

A MOS transistor manufacturing method, including: forming a first conductive or semiconductor layer; forming a sacrificial gate on the first layer and a second layer made of an insulating material laterally surrounding the sacrificial gate; forming, on either side of the sacrificial gate, source and drain electric connection elements crossing the second layer and contacting the first layer; removing the sacrificial gate and the portion of the first layer located vertically in line with the sacrificial gate; depositing a third layer made of a two-dimensional semiconductor material; depositing a fourth layer made of an insulating material on the third layer; and forming a conductive gate in the opening, on the fourth layer.

Forming of a MOS transistor based on a two-dimensional semiconductor material

A method for producing at least one pattern in a layer resting on a substrate, including: a) making amorphous at least one first block of an upper layer of crystalline material resting on a first amorphous supporting layer, while the crystalline structure of a second block of the upper layer that adjoins and is juxtaposed with the first block is preserved; b) partially recrystallizing the first block by using at least one side surface of the second block that is in contact with the first block as an area for the start of a recrystallization front, the partial recrystallization being carried out to preserve a region of amorphous material in the first block; c) selectively etching the amorphous material of the upper layer with respect to the crystalline material of the upper layer to form at least one first pattern in the upper layer.

Method for patterning a thin film

The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Method of making a transistor

Method for creation of stressed channel structure transistors wherein at least one amorphizing ion implantation of the surface layer of a substrate of the semiconductor-on-insulator type is carried out through openings in a mask, so as to render zones of the surface layers amorphous and to induce relaxation of a zone intended to form a channel and located between the zones that have been rendered amorphous, the relaxation being carried out in a direction orthogonal to that in which it is intended that the channel current flows.

Method of fabricating a transistor channel structure with uniaxial strain

A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox&#x3e;thk&#x2267;tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

Method for fabrication of a field-effect with reduced stray capacitance

A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.

SBFET transistor and corresponding fabrication process

A method is provided for producing a microelectronic device provided with different strained areas in a superficial layer of a semi-conductor on insulator type substrate, including amorphizing a region of the superficial layer and then a lateral recrystallization of the region from crystalline areas adjoining the region.

Method for producing a strained semiconductor on insulator substrate

A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting elements, the method including providing on a substrate at least one first semiconducting structure formed from a semiconducting stack including alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first material; then removing portions of the second material from the first semiconducting structure by selective etching, the removed portions forming at least one empty space; filling the empty space with a dielectric material; forming a straining zone on the first semiconducting structure based on a first strained material having an intrinsic strain; and performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the first material.

Method of modifying the strain state of a semiconducting structure with stacked transistor channels

A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

Transistor with MIS connections and fabricating process

The invention relates to a process for fabricating an integrated circuit (), comprising the steps of:

Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location

A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

Method for manufacturing a fin MOS transistor

FinFET transistor comprising portions of SiGe with a crystal orientation [111]

Growing community of inventors

Grenoble, France

Yves Morand