Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Institut National Des Sciences Appliquees De Lyon

Politecnico Di Torino

Yves Durand

Christian Bernard

Edith Beigne

Andrea Bocco

Daniele Jahier Pagliari

Massimo Poncino

Florent Dupont De Dinechin

Daniele Jahier-Pagliari

The present disclosure relates to a method of storing, by a load and store circuit or other processing means, a variable precision floating point value to a memory address of a memory, the method comprising: reducing the bit length of the variable precision floating point value to no more than a size limit, and storing the variable precision floating point value to one of a plurality of storage zones in the memory, each of the plurality of storage zones having a storage space equal to or greater than the size limit (MBB).

Method and device for floating point representation with variable precision

A direct memory access controller, configured to be used in a computing node of a system on chip (SoC), includes: (1) an input buffer for receiving packets of data coming from an input/output interface of the computing node; (2) a write control module for controlling writing of data extracted from each packet to a local memory of the computing node shared by at least one processor other than the direct memory access controller; and (3) an arithmetic logic unit for executing microprograms. The write control module is configured to control the execution by the arithmetic logic unit of at least one microprogram including instruction lines for arithmetic and/or logical calculation concerning only storage addresses for storing the data received by the input buffer for a reorganization of the data in the shared local memory. Optionally, at least one microprogram may be stored in a register, and at least two operating modes (e.g., restart mode and pause mode) of the at least one microprogram stored in the register may be configurable. Exemplary microprograms can (1) provide image processing parameters including sizes of columns of image blocks, (2) provide image processing parameters including numbers of successive pieces of data to be processed which are to be written to successive addresses in the shared local memory, and (3) utilize a sequential write mode and/or an absolute-offset write mode. Microprograms may be selected based on an identifier included in a header of each packet.

Direct memory access (DMA) controller, device and method using a write control module for reorganization of storage addresses in a shared local address space

The invention concerns a circuit comprising: a processing circuit () comprising a plurality of circuit domains (), each circuit domain () comprising a plurality of transistors and being configured to apply one or more corresponding transistor biasing voltages to said transistors; and a control circuit () configured to determine, based on at least a selected accuracy setting of the processing circuit, the level of said one or more transistor biasing voltages to be applied in each of said circuit domains, the control circuit () being further configured to cause said transistor biasing voltages to be applied to the circuit domains.

Processing circuit capable of dynamically modifying its precision

A method for dynamically controlling throughput set points from sources to targets in a network on a chip including a plurality of nodes and a plurality of links between these nodes for transmission of data packets, including for each link of the network solicited by the transmission of data packets, estimation of an available throughput margin that includes the estimation of a first margin calculated based on a maximum throughput capacity of the link; and for each emitting source of at least one data packet, the calculation and the application of an update of its throughput set point according to the estimated available throughput margins. Estimation of available throughput margin for each link includes estimation of a second margin calculated based on a maximum local absorption capacity of possible sporadic overflows of the throughput set points and its value is determined according to the first and second calculated margins.

Method for dynamically controlling throughput set points in a network on a chip, corresponding computer program and data processing device

The invention relates to an access controller which comprises a module () for managing writing in a circular buffer (), means () for storing a first read pointer (PL) and a second write pointer (PE), a module () for managing reading in the circular buffer (), means () for blocking reading, respectively writing, means () for storing a read or write work pointer (PT) which is different from the first and second pointers (PL; PE), and means () for updating the wo: pointer (PT) according to a predetermined update logic. The predetermined update logic comprises forward or backward movements of the work pointer (PT) inside the circular buffer (), and the controller includes means for blocking the read or write work pointer if the read work pointer (PT) points outside a memory space reserved for reading or, respectively, if the write work pointer (PT) points outside a free memory space for writing.

Direct memory access controller, corresponding method and computer program

A direct memory access controller including: a transfer module that transfers data from several data sources to at least one addressee for these data, through several buffer memories each including a predetermined number of successive elementary memory locations; a read management module that reads data stored in the buffer memories and that transfers them in sequence to the addressee; and a storage module that stores read pointers associated respectively with each buffer memory, each read pointer indicating an elementary location of the buffer memory with which it is associated and in which data can be read, wherein the buffer memories are associated respectively with each data source, and for each buffer memory, the controller includes means for executing a firmware that reads data and updates a read pointer associated with this buffer memory, and for synchronising execution of the firmwares as a function of a predetermined order of data originating from buffer memories required in a data sequence to be transferred to the addressee.

Growing community of inventors

Saint-Ismier, France

Yves Durand