Stmicroelectronics (crolles 2) Sas

Stmicroelectronics S.a.

Other

France Telecom

France T&eacute;l&eacute;com

International Business Machines Corporation

Centre National D'etudes Des Telecommunications

Yves Campidelli

Daniel Bensahel

Caroline Hernandez

Olivier Kermarrec

Yves Morand

Maurice Rivoire

Oliver Kermarrec

Didier Dutartre

Fran&ccedil;ois Martin

Vincent Cosnier

Olivier Kermarec

Nicolas L Breil

Alexis Gauthier

Aomar Halimaoui

Denis Pellissier-Tanon

David Barge

Olivier Gourhant

Philippe Garnier

Fabien Deprat

Guillaume Pin

Roland Pantel

Francois Arnaud D'Avitaya

Francois A d'Avitaya

Zahra Aitfqirali-Guerry

A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

Cyclic epitaxy process to form air gap isolation for a bipolar transistor

An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Method for fabricating NMOS and PMOS transistors on a substrate of the SOI, in particular FDSOI, type and corresponding integrated circuit

A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Process for producing at least one deep trench isolation

A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.

Method for depositing a silicon oxide layer of same thickness on silicon and on silicon-germanium

A single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Single-crystal semiconductor layer with heteroatomic macro-network

A method for manufacturing an insulated semiconductor layer, including: forming a porous silicon layer on a single-crystal silicon surface; depositing an insulating material so that it penetrates into the pores of the porous silicon layer; eliminating the insulating material to expose the upper surface of the porous silicon; and growing by epitaxy a semiconductor layer.

Method for manufacturing a structure of semiconductor-on-insulator type

The invention relates to a single-crystal layer of a first semiconductor material including single-crystal nanostructures of a second semiconductor material, the nanostructures being distributed in a regular crystallographic network with a centered tetragonal prism.

Single-crystal semiconductor layer with heteroatomic macronetwork

A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.

Electronic component manufacturing method

A system and method for producing a single-crystal germanium layer on a dielectric layer by producing a germanium-on-insulator assembly between the surface portions of the third material. The choice of location for these surface portions therefore makes it possible to define the zone on which it is desired to produce the germanium-on-insulator layer. The wafer may be freely chosen between a pure single-crystal silicon wafer and a silicon-on-insulator wafer. A single-crystal germanium first layer is produced on the surface portion of the silicon. The RPCVD produces a partially crystalline germanium first layer. The layer thus comprises various nuclei that have crystallized in possibly different lattices. After carrying out a recrystallization annealing operation, which makes the layer monocrystalline by recrystallizing the various nuclei in one and the same crystal lattice. Thus, the layers are continuous with the single-crystal silicon lattice.

Single-crystal layer on a dielectric layer

The process relates to the production of a layer of a single-crystal first material on a second material. The second material has at least one aperture exposing a surface portion of a single-crystal third material. The process generally includes forming an at least partially crystalline first layer of said first material on said surface portion of the third material. Then, an amorphous or partially crystalline second layer of the first material is formed on the at least partially crystalline first layer of the first material and on one part of the second material that is around said aperture. Finally, the process includes recrystallization annealing of the first material. Thus, it is possible to produce, within one and the same wafer, either transistors on a germanium-on-insulator substrate with transistors on a silicon-on-insulator substrate, or transistors on a germanium-on-insulator substrate with transistors on a silicon substrate.

A method for forming, by epitaxy, a heteroatomic single-crystal semiconductor layer on a single-crystal semiconductor wafer, the crystal lattices of the layer and of the wafer being different, including forming, before the epitaxy, in the wafer surface, at least one ring of discontinuities around a useful region.

Heteroatomic single-crystal layers

A process and a device for fabricating a semiconductor device having a gate dielectric made of high-k material, includes a step of depositing, directly on the gate dielectric, a first layer of SiGe, where 0.5&#x3c;x&#x2266;1, at a temperature substantially below the temperature at which a poly-Si is deposited by thermal chemical vapor deposition (CVD).

Method of fabricating a semiconductor device comprising a gate dielectric made of high dielectric permittivity material

A method for forming on a Ge or Si monocrystalline substrate successive Si/Ge, Si/SiGe, or Si/SiGe/Ge layers for a Ge substrate and inversely for a Si substrate is described. Electrochemical treatment of the stack of layers to make the layers porous and form therein residual crystallites is also described. The invention may be used to provide devices having layers of planes of quantum drops.

Method for making a device comprising layers of planes of quantum dots

A method of forming, on a single-crystal semiconductor substrate of a first material, quantum dots of a second material, including growing by vapor phase epitaxy the second material on the first material in optimal conditions adapted to ensuring a growth at a maximum controllable rate. In an initial step, a puff of a gas containing the second material is sent on the substrate, in conditions corresponding to a deposition rate much faster than the maximum controllable rate.

Forming of quantum dots

The invention concerns a method which consists in: (a) stabilization of the monocrystalline silicon substrate temperature at a first predetermined temperature T of 400 to 500&deg; C.; (b) chemical vapour deposition (CVD) of germanium at said first predetermined temperature T until a base germanium layer is formed on the substrate, with a predetermined thickness less than the desired final thickness; (c) increasing the CVD temperature from said first predetermined temperature T up to a second predetermined temperature T of 750 to 850&deg; C.; and (d) carrying on with CVD of germanium at said second predetermined temperature T until the desired final thickness for the monocrystalline germanium final layer is obtained. The invention is useful for making semiconductor devices.

Growing community of inventors

Grenoble, France

Yves Campidelli