Hitachi, Ltd.

Other

Renesas Technology Corp.

Yuzuru Ohji

Shinpei Iijima

Yasuhiro Sugawara

Isamu Asano

Hiroyuki Ohta

Yoshitaka Nakamura

Nobuyoshi Kobayashi

Masahiko Hiratani

Yuichi Matsui

Takashi Yunogami

Hiroshi Miki

Shinichi Tachi

Takuya Fukuda

Ryouichi Furukawa

Misuzu Kanai

Tomio Iwasaki

Kazuo Nojiri

Hiroshi Moriya

Hirohiko Yamamoto

Sukeyoshi Tsunekawa

Yukihiro Kumagai

Akira Takamatsu

Tadanori Yoshida

Masato Kunitomo

Naruhiko Nakanishi

Masayuki Ishizaka

Shinpei Iljima

Toshio Uemura

Sinpei Iijima

Tomonori Sekiguchi

Satoru Yamada

Hitoshi Kume

Toshiyuki Mine

Tokuo Kure

Tsugio Takahashi

Yoshitaka Tadaki

Kunio Harada

Hiroshi Kanda

Tatsuyuki Saito

Tetsuo Adachi

Yasuhiro Mitsui

Hiroshi Kawakami

Isao Ishikawa

Osamu Kasahara

Hideharu Yahata

Shiro Kamohara

Hiroko Kaneko

Masayoshi Hirasawa

Kyoichiro Asayama

Keiichi Kanehori

Masahiro Ushiyama

Sumio Yamaguchi

Kunihiro Yagi

Fumiko Arakawa

A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

Semiconductor memory with strongly adhesive electrode

Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 &#x3bc;m or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 &#x3bc;m to 0.8 &#x3bc;m to the first electrode pad.

Method of manufacturing a semiconductor device to provide a plurality of test element groups (TEGs) in a scribe region

Semiconductor device with adhesion-improvement capacitor and process for producing the device

Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode made of ruthenium, a capacitor insulating film made of BST and an upper electrode , the upper electrode has a laminate structure comprising a ruthenium film formed on the side of the capacitor insulating film and a tungsten film formed over the former.

Semiconductor integrated circuit device having spaced-apart electrodes and the method thereof

A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

CAPACITOR STRUCTURE AND A SEMICONDUCTOR DEVICE WITH A FIRST METAL LAYER, A SECOND METAL SILICIDE LAYER FORMED OVER THE FIRST METAL LAYER AND A SECOND METAL LAYER FORMED OVER THE SECOND METAL SILICIDE LAYER

A first silicon film is so formed as to extend along the inner surface of trenches formed in a silicon oxide film , an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode of a capacitance device can be lowered.

HSG semiconductor capacitor with migration inhibition layer

A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode a capacitor insulator and an upper electrode wherein the lower electrode is made of a conductive material containing ruthenium dioxide (RuO ) as principle ingredient and the capacitor insulator is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

Semiconductor integrated circuit device and method of manufacturing the same

A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode , a capacitor insulator and an upper electrode , wherein the lower electrode is made of a conductive material containing ruthenium dioxide (RuO ) as principle ingredient and the capacitor insulator is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

Semiconductor integrated circuit device with information storage capacitor having ruthenium dioxide lower electrode and crystallized TA2O5 capacitor insulator

Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.

Semiconductor device comprising capacitor cells, bit lines, word lines, and MOS transistors in a memory cell area over a semiconductor substrate

METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON NITRIDE LAYER TO PROTECT AN UNDERLYING METAL SILICIDE LAYER FROM OXIDATION DURING SUBSEQUENT PROCESSING STEPS

A first silicon film is so formed as to extend along the inner surface of trenches formed in a silicon oxide film an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode of a capacitance device can be lowered.

Semiconductor device and method of fabricating the same

Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.

Method of manufacturing a semiconductor integrated circuit

After formation of a groove in a silicon oxide film, a Pt film is formed inside of the groove by electroplating using a conductive underlying film, which has been formed in advance below the silicon oxide film, as a cathode electrode. The silicon oxide film is then removed by etching, followed by dry etching of the conductive underlying film with the Pt film as a mask, whereby a lower electrode of a capacitor is formed from the Pt film and the conductive underlying film which has remained below the Pt film.

Process for making a semiconductor integrated circuit device having a dynamic random access memory

A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Semiconductor integrated circuit device

Semiconductor integrated circuit and its manufacturing method

Growing community of inventors

Hinode, Japan

Yuzuru Ohji