Fujitsu Corporation

Yuzo Ageno

Kaneyasu Shimoda

Tadayoshi Katoh

A sequential decoder for decoding a systematic and convolutional code signal having a code rate greater than 1/2 and carrying out error correction coding of the code signal. A local most likely path in a plurality of possible paths for a newly received information bit is determined by calculating a branch metric indicating likelihood of each of the plurality of possible paths in accordance with a predetermined algorithm. The path decision is carried out by a construction including a two-path comparing path decision circuit which receives a pair of bits comprised of an information bit and a parity bit at one time and determining a local most likely path between two possible paths for the information bit. A four-path comparing path decision circuit receives a pair of information bits at one time and determines a local most likely path among four possible paths for the pair of information bits. A parity bit timing detecting circuit detects a timing of an input of the above pair of bits comprised of an information bit and a parity bit. A selecting circuit selects an output of the above two-path comparing path decision circuit at the input timing of the above pair of bits comprised of an information bit and a parity bit, and selects an output of the above four-path comparing path decision circuit at the timing of the input of the above pair of information bits.

Sequential decoder

A sequential decoding device for decoding a data expressed by a systematic code having a symbol memory, a maximum likelihood path decision circuit, and a path memory, includes: an overflow detection circuit for detecting an overflow of the symbol memory, and a switch for supplying signal bit data, as an decoded output, read from the symbol memory directly to the path memory in correspondence with an overflow detection signal from the overflow detection circuit. The device includes further a path metric value increase/decrease monitoring circuit for monitoring the increase/decrease of a path metric value delivered from the maximum likelihood path decision circuit and controlling the switch in such a manner that, when a monotonous increase of path metric value is detected, the decoded output of the maximum likelihood path decision circuit is supplied to the path memory instead of a direct supply of the decoded output of the symbol memory to the path memory.

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Yokohama, Japan

Yuzo Ageno