Fujitsu Corporation

Shimadzu Corporation

Yuzi Kanazawa

Shinji Kanazawa

Hiroyuki Yasuda

Yohei Yamada

Yusuke Hida

Akihiro Kunisawa

Takeshi Osoekawa

Yoshihiro Tsuchiya

Hiroyuki Higuchi

Tsuneo Nakata

Tsutomu Ishida

Yu Liu

Hidetoshi Terada

Takahide Yoshikawa

An analyzer configured to acquire a chromatogram or spectrum by performing a predetermined analysis of a sample and perform a qualitative or quantitative analysis of components contained in the sample. The analyzer includes: a peak detection unit configured, based on information regarding a plurality of target components that need to be checked whether contained in the sample or that need to be quantified, to detect a peak or peaks in the chromatogram or spectrum acquired by the predetermined analysis of the sample corresponding to one of the target components, configured to acquire peak information regarding each of the peak or peaks, and configured to obtain confidence information for each of the peak or peaks, the confidence information being an indicative value of certainty of detecting a peak; and a display processing unit configured to display on a display unit a list of at least a part of the target components.

Analyzer configured to display list of target components

When chromatogram data for a target sample have been acquired, a peak position estimator determines an estimated result of the position of the starting and/or ending point of a peak as well as the confidence value representing the reliability of the estimation, using a trained model stored in the trained model storage section. Normally, a plurality of estimated results of the starting point and/or ending point of the peak are acquired for one peak. A peak information correction processor identifies a candidate having the highest confidence as a prime candidate, and superposes a plurality of candidates including the prime candidate, with their respective confidence values, on a displayed chromatogram. An operator referring to the confidence values selects a peak which needs close checking or correction, and corrects the starting point and/or ending point of the selected peak, for example, by selecting and indicating a candidate other than the prime candidate.

Waveform analyzer

A model constructed by a training process using the technique of deep learning using the training data including images created from a large number of chromatograms and correct peak information is previously stored in a trained model storage section. When chromatogram data for a target sample acquired with an LC measurement unit are inputted, an image creator converts the chromatogram into an image and creates an input image in which one of the two areas divided by the chromatogram curve as the boundary in the image is filled. A peak position estimator inputs the pixel values of the input image into a trained model using a neural network, and obtains the position information of the starting point and/or ending point of the peak and a peak detection confidence as the output. A peak determiner determines the starting point and/or ending point of each peak based on the peak detection confidence.

A disclosed method includes: converting, for each sample point, a set of performance item values for a sample point into coordinate values of a mesh element containing the set among plural mesh elements obtained by dividing a space mapped by the performance items; generating a binary decision graph representing a group of the coordinate values of the sample points; calculating the number of sample points including second sample points that dominates a first sample point and the first sample point, by counting the number of paths in the binary decision graph from a root node to a leaf node representing '1' through at least one of certain nodes corresponding to coordinate values that are equal to or less than coordinate values of the first sample point; and calculating a yield of the first sample point by dividing the calculated number by the number of the plural sample points.

Method and apparatus for calculating yield

Among the combinations of failure candidates which combinations are generated by a generator, one combination that minimizes a cost derived in a cost calculator is selected. For the selected combination of failure candidates, a function, which specifically provides a correlation between one or more failure factor and an error (or error rate) of each failure element is output. A correct failure factor is estimated on the basis of the function.

Non-transitory computer-readable recording medium in which a failure analyzing program is recorded, failure analyzing apparatus, and method for analyzing failure

A processing unit includes: a cache memory including a plurality of memory elements; an error detection circuit configured to detect an error when a first timing for reading data from the cache memory is behind a threshold; a latch circuit configured to set a second timing for latching the data based on an output from the error detection circuit and to latch the data at the second timing; and a processing unit core to process the data latched by the latch circuit.

Processing unit

A leak current calculation apparatus includes an acquiring section for acquiring partial circuit information, and a grouping section for forming a plurality of groups each comprising a part of the partial circuits connected with each other and for generating group information. The apparatus includes a leak difference value calculating section for calculating a leak difference value, which is a difference between a provisional maximum value acquired by adding up the maximum values of the leak current values of all the partial circuits and a sum of maximum values of the leak current values contained in the group information of the groups, and a maximum leak current calculating section for calculating the maximum leak current value of the integrated circuit by adjusting the provisional maximum value with the leak difference value.

Leak current calculation apparatus and method for calculating leak current

In order to confirm a propagation range of a signal whose signal value is fixed by a control signal to restrain switchings is within a predetermined range, it is judged by results of the logic simulation whether or not a switching restraining mode is enabled. If it is enabled, a switching probability restraint information list including the detected time and an ID of the net whose signal value is fixed is set to the net whose signal value is fixed, and then is propagated to the next net according to the results of the logic simulation. If the circuit changes are appropriated conducted, the results of the logic simulation do not satisfy the propagation condition of the switching probability restraint information list. Accordingly, the switching probability restraint information list is not propagated over the predetermined range, and no problem is detected.

Circuit operation verification method and apparatus

An information processing system includes a management apparatus having a transmission preventing part preventing transmission of a predetermined usage allowing signal allowing usage of a predetermined device, in response to receiving a predetermined usage preventing instruction for the predetermined device.

Information processing system

The circuit volume of a system under design is reduced by a circuit conversion involving consolidation (sharing) of common parts in the system by a representative part. The design data of the system post-conversion is used to verify operation of the system. However, the verification results for the system post-conversion express signals (e.g., signal X) of plural modules (e.g., modules a to c) as one signal waveform thereby making debugging difficult when a bug is found. Given this situation, from the verification results of the system post-conversion, signal-generation-use data is generated for generating the signal waveforms (here, respective signal waveforms for the modules a to c) of the system before conversion. After verification is complete, a signal waveform for each of the modules a to c is generated using the verification results for the system under design and the signal-generation-use data.

Verification support apparatus, verification support method, and computer product

Design data of a cell group is copied to obtain design data of an antecedent cell group and of a subsequent cell group. Design data of a combinational circuit is copied to generate the combinational circuits in plural corresponding to a given number of cycles n (n=2, 3, 4 . . . , where n=3 in FIG.). The design data of the combinational circuits are connected in series between the design data of the antecedent cell group and the design data of the subsequent cell group. As a result, design data of an input constraint circuit representing an input constraint(s) of the circuit can be generated.

Apparatus, method, and computer product for estimating power consumption of LSI

A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.

Circuit design data conversion apparatus, circuit design data conversion method, and computer product

In manufacturing a structured ASIC, after production of an intermediate product with a transistor layer or the transistor layer and a metal layer, the transistor speed of each intermediate product is measured and, using the speed and associated statistical data, a maximum transistor speed delay is estimated. Based on the estimate, the type of the structured ASIC is determined from among an existing list of LSI circuit types.

Method and apparatus for determining LSI type, method and apparatus for supporting LSI design, and computer product

After a provisional layout in a sub-module of a semiconductor integrated circuit is performed, a path optimizing inter-sub-modules process is executed, and the layout and wiring among sub-modules are performed. If any part of the wiring among sub-modules does not satisfy a specified delay restriction, a provisional-layout correction process is executed to correct the provisional layout of cells in a sub-module. These processes are repeated, and then an entire layout of cells is determined.

LAYOUT INSTRUMENT FOR SEMICONDUCTOR INTEGRATED CIRCUITS, LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUITS AND RECORDING MEDIUM THAT STORES A PROGRAM FOR DETERMINING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUITS

A restricted region managing module accepts for management a restricted region and its cell maximum activity ratio &rgr;max specified by a restricted region specifying module. A cell placing module places cells in such a manner that a cell activity ratio &rgr; of the restricted region managed by the restricted region managing module does not exceed the specified cell maximum activity ratio &rgr;max.

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Kawasaki, Japan

Yuzi Kanazawa