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Agere Systems Inc.

Yuzheng Ding

Peter Ramyalal Suaris

Nan-Chi Chou

Lung-Tien Liu

Miron Abramovici

Barry Britton

Harold Scholz

Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.

Memory re-implementation for field programmable gate arrays

Signals sent from one system-on-chip core become switched to a reconfigurable logic core (RLC) for observation and, perhaps, replacement with another signal. A first signal line couples together a plurality of cores. A switch, disposed between the first signal line and an input signal line of the RLC, selectively controls whether the signal gets sent to the RLC. A multiplexer, having the first signal line and an output signal line of the RLC as inputs, selectively controls whether the signal or a replacement signal becomes conveyed to another core of the system-on-chip. Observation and control configuration memory bits act as inputs in the selective control of the switch and the multiplexer. Other embodiments teach shared RLC input signal lines amongst multiple cores. The RLC may contain an inverter, a test circuit, a logic analyzer or other. Methods of observing and replacing signals are also taught.

Programmable interconnect for reconfigurable system-on-chip

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Berkeley Heights, NJ, United States of America

Yuzheng Ding