Intel Corporation

Tahoe Research, Ltd.

Yuxin Bai

Victor W Lee

Daehyun Kim

Naveen K Mellempudi

Sheng C Li

Dhiraj D Kalamkar

Edward Thomas Grochowski

Shihao Ji

Sheng Li

In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

Performing power management in a multicore processor

In one embodiment, A processor includes a logic to receive performance monitoring information from at least some of a plurality of cores and determine, according to a power management model, a performance state for one or more of the plurality of cores based on the performance monitoring information, and a second logic to receive the performance monitoring information and dynamically update the power management model according to a reinforcement learning process. Other embodiments are described and claimed.

Dynamically updating a power management policy of a processor

In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.

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