Intel Corporation

Other

Fortinet, Inc.

Intel IP Corporation

Yuwei Zhang

Prasanna Desai

Jun Lu

Assaf Gurevitz

Oren Kaidar

Shushan Wen

Anthony Tsangaropoulos

Jinyong Lee

Sharon Heruti

Shue-Lee Chang

Kevin Hwang

Thomas W Brown

Chen Meng

A CRC rule is generated for each CRC parity check circuit from a bank of CRC parity check circuits for mapping a fixed-length CRC output to a signature, each of the CRC parity check circuits servicing a specific string length. The selected CRC parity circuit outputs a fixed-length parity-check data for the specific data packet, and the string mapper maps the fixed-length parity-check data for the specific data packet to one of the string identifiers associated with the group of signatures. If a fixed-length parity-check match is found, outputting a string identifier of the match for a security action.

Intrusion protection system (IPS) for hash-based string detection without memory lookup table

In one embodiment, an apparatus of a wireless communication device includes control circuitry to cause receiver circuitry of the wireless communication device to switch between an on-mode and an off-mode. The apparatus also includes synchronizing circuitry to: perform a correlation on signals of a packet received by the receiver circuitry when in the on-mode to detect a pattern in the received signals, and cause the control circuitry to hold the receiver circuitry in the on-mode based on detection of the pattern in the received signals. The apparatus further includes demodulation circuitry to process additional signals of the packet received by the receiver circuitry when held in the on-mode.

Time slotted scan receiver

A method and apparatus for synchronizing a wireless communication receiver such as a Bluetooth receiver, including estimating the condition of the communication channel and operating the receiver either in frequency domain mode or in time domain mode based on the channel condition estimation. A soft threshold is used to estimate the symbols of the access address code. Oversampled data rate received data is processed at symbol rate of the data. Receiver functions are terminated upon determining that no signal that the receiver can decode is being received. Synchronization includes a correlator that processes an entire address code or a correlator that processes the address code in segments.

Method and apparatus for low power synchronization of bluetooth systems

For example, a wireless communication device may be configured to determine a count of one or more unreliable data symbols in a received wireless communication packet having a valid Cyclic Redundancy Check (CRC) result; based on the count of the unreliable data symbols, to determine whether to classify the valid CRC result as a false-positive CRC result; and, based on classification of the valid CRC result as a false-positive CRC result, to handle the received wireless communication packet as having a non-valid CRC result.

Apparatus, system and method of processing a wireless communication packet based on a cyclic redundancy check (CRC) result

A synchronizer can include a symbol estimator, an inner-pattern de-mapper, a timing tracker, and a correlator. The symbol estimator can be configured to estimate one or more symbols of a received signal based on a phase signal. The inner-pattern de-mapper can be configured to de-map the one or more symbols to generate an inner-pattern de-mapped symbol estimation. The timing tracker can be configured to accumulate the inner-pattern de-mapped symbol estimation and to determine a peak position based on the accumulated inner-pattern de-mapped symbol estimation. The correlator can be configured to correlate the accumulated inner-pattern de-mapped symbol estimation based on a reference signal. The correlation of the accumulated inner-pattern de-mapped symbol estimation can be independent of a signal over sampling rate (OSR). The synchronizer can be adapted in a long range Bluetooth low energy (BLE) receiver.

Long range bluetooth low energy synchronization system

A trellis coded modulator and method for generating an encoded word from an input word. The TCM has a first logic branch configured to generate a data portion of the encoded word; and a second logic branch, coupled in parallel with the first logic branch, and configured to generate a corresponding parity portion of the encoded word sequentially after the generation of the data portion of the encoded word.

Trellis coded modulation

A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.

Decision feedback equalization with composite trellis slicer

A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.

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Pleasanton, CA, United States of America

Yuwei Zhang