Dell Products Inc.

Yuwei Cai

Michael D Christensen

Amit Shah

Mark Dykstra

An information handling system includes a memory, and a basic input/output system (BIOS). The BIOS receives a request to map multiple processor cores to multiple integrated memory controllers of a multiple core processor. In response to the reception of the request, the BIOS calculates a different latency for each of the processor cores. Based on the calculated different latency for each of the processor cores, the BIOS assigns mapping priority levels to the processor cores of the multiple core processor. Based on the mapping priority levels, the BIOS maps each of the processor cores to an associated one of the integrated memory controllers. The BIOS stores the map of the processor cores in the memory.

Core mapping based on latency in a multiple core processor

An information handling system includes a model-specific register and a basic input/output system (BIOS). The BIOS receives a selection of a number of processor cores to have enabled in a multiple core processor. In response to the reception of the selection of the number of processor cores to have enabled, the BIOS calculates a different latency for each of a plurality of processor cores in the multiple core processor. Based on the calculated different latency for each of the processor cores, the BIOS determines a first subset of the processor cores to enable and a second subset of the processor cores to disable. The BIOS sets bits in the model-specific register to indicate that the first subset of the processor cores is enabled and the second subset of the processor cores is disabled.

Disabling processor cores for best latency in a multiple core processor

An information handling system includes a memory controller with an error logger, and a DIMM coupled to the memory controller via a memory channel. The DIMM includes a non-volatile memory device mapped to include event blocks that store error information associated with memory events occurring the memory controller, the DIMM, and the memory channel. Each event block includes a flag field and a data field. The error logger receives an indication that a memory event has occurred, reads first flag information from a flag field of an event block, determines whether the event block is locked based upon the first flag information, and if the event block is not locked, then writes second flag information to the flag field and writes event information to a data field of the event block. The event information describes the memory event.

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Austin, TX, United States of America

Yuwei Cai