Eye-fi, Inc.

Silicon Graphics, Incorporated

Silicon Graphics International Corporation

Yuval Koren

Eugene Feinberg

Berend Ozceri

Givargis George Kaldani

Martin M Deneroff

David Edward McCracken

Ziv Gillat

Swami Venkataraman

Earl T Cohen

Asgeir Thor Eiriksson

Doug Solomon

Swaminatham Venkataraman

A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated.

Content-aware digital media storage device and methods of using the same

A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated.

In one embodiment, the invention provides a method for configuring a wireless device, so as to enable the wireless device to join a secured wireless network, by broadcasting a series of broadcast packets encoding a network configuration parameter (e.g., a shared secret key) from a computer coupled to a wireless access point to the wireless device. The information representing the network configuration parameter is encoded, not within the payload portion of the packet, but within the length of each broadcast packet in the series of broadcast packets. Accordingly, a wireless device that has not yet been configured to receive packets from the wireless access point can observe the information encoded in the length of each broadcast packet, and thereby decode the network configuration parameter and join the network.

In-band device enrollment without access point support

A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.

Multiprocessor node controller circuit and method

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.

A method and apparatus for purging data from a middle cache level without purging the corresponding data from a lower cache level (i.e., a cache level closer to the processor using the data), and replacing the purged first data with other data of a different memory address than the purged first data, while leaving the data of the first cache line in the lower cache level. In some embodiments, in order to allow such mid-level purging, the first cache line must be in the &ldquo;shared state&rdquo; that allows reading of the data, but does not permit modifications to the data (i.e., modifications that would have to be written back to memory). If it is desired to modify the data, a directory facility will issue a purge to all caches of the shared-state data for that cache line, and then the processor that wants to modify the data will request an exclusive-state copy to be fetched to its lower-level cache and to all intervening levels of cache. Later, when the data in the lower cache level is modified, the modified data can be moved back to the original memory from the caches. In some embodiments, a purge of all shared-state copies of the first cache-line data from any and all caches having copies thereof is performed as a prerequisite to doing this exclusive-state fetch.

Method and cache-coherence system allowing purging of mid-level cache entries without purging lower-level cache entries

A computer system ( ) includes a node controller ( ) operable to process invalidation requests. The node controller ( ) includes a network interface unit ( ), a memory directory interface unit ( ), a processor interface unit ( ), an input/output interface unit ( ), a local buffer unit ( ), and a crossbar unit ( ). A local processor ( ) generates an invalidation request that is processed by the processor interface unit ( ) for placement into the local buffer unit ( ). The invalidation request indicates that particular data within a local memory ( ) associated with the node controller ( ) has been altered by the local processor ( ). The local buffer unit ( ) generates a plurality of invalidation messages in response to the invalidation request, the invalidation messages being destined for remote processors ( ) associated with remote node controllers ( ) in the computer system ( ) that share the particular data. The crossbar unit ( ) arbitrates the transfer of the invalidation messages with data, control messages, and other traffic to and from all units associated with the node controller ( ) so that the node controller ( ) is not clogged with the transfer of invalidation messages.

Growing community of inventors

San Francisco, CA, United States of America

Yuval Koren