Nuvoton Technology Corporation

Yuval Kirschner

Ziv Hershman

Michal Schramm

Tamir Golan

Nir Tasher

Moshe Alon

Victor Adrian Flachs

Ilia Stolov

Nimrod Peled

Arnon Sharlin

Ofer Cohen

Erez Naory

An integrated circuit (IC) includes a thermal memory device, a fault injection (FI) detector and a security control circuit. The thermal memory device includes (i) a thermal storage zone and (ii) a heating element configured to heat the thermal storage zone in response to write operations. The FI detector is configured to detect attempts to inject faults into the IC. The security control circuit is configured to perform a write operation to the thermal memory device in response to an attempt detected by the FI detector, to identify a sequence of the attempts that meets a density criterion, by reading the thermal memory device, and initiate a responsive action upon identifying the sequence.

Tracking and prevention of fault injection attempt sequences using thermal memory

An integrated circuit (IC) includes a non-volatile memory and boot circuitry. The boot circuitry is configured to boot the IC, including reading from the non-volatile memory one or more values indicative of whether production testing of the IC was completed successfully, and initiating a responsive action if the one or more values indicate that the production testing was not completed successfully.

Fail-safe IC production testing

A computer system includes a memory, a processor and authentication enforcement hardware. The processor is configured to execute software, including an authentication program that authenticates data stored in the memory. The authentication enforcement hardware is coupled to the processor and is configured to verify that (i) the processor executes the authentication program periodically with at least a specified frequency, and that (ii) the authentication program successfully authenticates the data.

Forced self authentication

A secure Integrated Circuit (IC) includes functional circuitry, and protection circuitry configured to protect the functional circuitry against fault-injection attacks. The protection circuitry includes a plurality of digital detection cells, and protection logic. The detection cells have respective inputs and outputs and are connected output-to-input in at least a chain. In response to a fault-injection attack, a given detection cell in the chain is configured to toggle an output that drives an input of a subsequent detection cell in the chain, thereby causing a pulse to propagate along the chain. The protection logic is configured to receive the pulse from the chain and initiate a responsive action.

Digital fault injection detector

A Random-Number Generator (RNG) includes a first plurality of High-Frequency (HF) clock generators, a second plurality of Low-Frequency (LF) clock generators, a third plurality of Digital Random-Number Generator circuits (DRNGs), and a multiplexer. The HF clock generators are configured to generate respective HF clock signals in a first frequency range. The LF clock generators are configured to generate respective LF clock signals in a second frequency range, lower than the first frequency range. Each DRNG is configured to derive a respective random-bit sequence from (i) a respective HF clock signal taken from among the HF clock signals and (ii) a respective LF clock signal taken from among the HF clock signals. The multiplexer is configured to produce an output sequence of random bits from random-bit sequences generated by the DRNGs.

Distributed random-number generator

Described embodiments include a system, including clocked circuitry, an oscillator controller, and an oscillator, configured to output an output clock signal that clocks the clocked circuitry and is fed to the oscillator controller. The oscillator controller is configured to control the oscillator responsively to an output frequency of the output clock signal. The system further includes power-management circuitry, configured to cause the clocked circuitry to sleep by disabling the oscillator, and waking circuitry, configured to intermittently enable the oscillator such that the oscillator controller intermittently, while the clocked circuitry sleeps, causes the output frequency to converge to a target frequency by controlling the oscillator. Other embodiments are also described.

Intermittent tuning of an oscillator

An electronic apparatus includes, a substrate, one or more routing layers, and an active shield layer. The substrate includes active devices. The routing layers are electrically connected to the active devices and are configured to route electrical signals to and from the active devices. The active shield layer is disposed within a routing layer nearest to the substrate, the active shield layer includes metallic traces configured conduct active-shield signals that provide an indication of an attack on the apparatus.

Active shield for protecting a device from backside attacks

An electronic circuit includes a first oscillator, a second oscillator and ancillary circuitry. The first oscillator is configured to generate a first clock signal and has a first wake-up delay. The second oscillator is configured to generate a second clock signal and has a second wake-up delay that is shorter than the first wake-up delay. The ancillary circuitry is configured to provide the second clock signal as an output clock signal during wake-up of the first oscillator, and, following the first wake-up delay, to provide the first clock signal as the output clock signal.

Mitigation of long wake-up delay of a crystal oscillator

An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

Growing community of inventors

Even Yehuda, Israel

Yuval Kirschner