Western Digital Technologies, Inc.

Yuval Grossman

Tomer Tzvi Eliash

Alexander Bazarsky

David Chaim Brief

Asaf Gueta

Inon Cohen

Shlomo Naidorf

Yehuda Hahn

Yoav Markus

Jonathan Sokolowski

Ofer Privman

Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.

Multiple sets of trim parameters

Disclosed are systems and methods for efficient power management for storage devices. A method includes receiving a request to transition a flash memory to a first stand-by mode, wherein the flash memory comprises a plurality of dies. The method also includes causing one or more guard dies of the plurality of dies to transition to the first stand-by mode while causing one or more other dies of the plurality of dies to transition to a second stand-by mode, wherein the second stand-by mode is configured to consume less power than the first stand-by mode. The method also includes receiving an input/output (I/O) request for the flash memory. The method also includes causing the I/O request to be performed on the one or more guard dies that are in the first stand-by mode but not in the second stand-by mode.

Efficient power management modes for multiple memory devices

Apparatus, media, methods, and systems for data storage systems and methods for optimized scheduling of background management operations. A data storage system may comprise a controller. The controller is configured to determine a timeout value of an adaptive timeout parameter of the data storage system. The controller is configured to determine whether a first host operation is received. The controller is configured to, when the first host operation is not received, determine whether the timeout value satisfies a threshold value. The controller is configured to, when the timeout value satisfies the threshold value, cause one or more background management operations to be executed at the data storage system.

Data storage systems and methods for optimized scheduling of background management operations

A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

Measurement, calibration and tuning of memory bus duty cycle

Disclosed are systems and methods for providing an improved hardware-assisted multi-table database with reduced memory footprint. A method includes receiving a request to perform an operation on a selected logical table of a plurality of logical database tables. The method also includes accessing a data structure comprising a plurality of records each including: a logical table identifier corresponding to one of the plurality of logical database tables, wherein the logical table identifier is accessed from a register, and at least one sort key. The method also includes performing the operation using one or more sort criteria, wherein the one or more sort criteria are maintained for the selected logical table using the at least one sort key of the plurality of records corresponding to the selected logical table. The method also includes updating the data structure to reflect the performed operation.

Hardware-assisted multi-table database with shared memory footprint

The present disclosure generally relates to relocating data in a storage device and updating a compressed logical to physical (L2P) table in response without invalidating cache entries of the L2P table. After relocating data from a first memory block associated with a first physical address to a second memory block associated with a second physical address, a version indicator of a cache entry corresponding to the first physical address in the L2P table is incremented. One or more cache entries are then added to the L2P table associating the relocated data to the second physical block without invaliding the cache entry corresponding to the first physical address. When a command to read or write the relocated data is received, the storage device searches the L2P table and reads the data from either the first memory block or the second memory block.

Optimized handling of multiple copies in storage management

Efficient power management stand-by modes for multiple dies in a storage device

A system and method for storage system property deviation are provided. In one embodiment, a storage system is presented comprising a memory and a controller configured to: receive a request from a host to modify a write parameter used to write data to the memory; write data to the memory using the modified write parameter; restore the write parameter to its pre-modified state; and re-write the data to the memory in a background operation using the write parameter in its pre-modified state. Other embodiments are provided.

System and method for storage system property deviation

A storage system and method for adaptive scheduling of background operations are provided. In one embodiment, after a storage system completes a host operation in the memory, the storage system remains in a high power mode for a period of time, after which the storage system enters a low-power mode. The storage system estimates whether there will be enough time to perform a background operation in the memory during the period of time without the background operation being interrupted by another host operation. In response to estimating that there will be enough time to perform the background operation in the memory without the background operation being interrupted by another host operation, the storage system performs the background operation in the memory.

Growing community of inventors

Kiryat Ono, Israel

Yuval Grossman