Sony Semiconductor Solutions Corporation

Sony Corporation

Yuusuke Nishida

Yasuaki Hisamatsu

Norihiro Nikai

Hayato Gouji

The disclosure relates to a solid-state imaging element, a method of operating the solid-state imaging element, an imaging apparatus, and an electronic device. The solid-state imaging element enables appropriate measurement of fluctuation of power supply voltage, and removal of noise caused by the fluctuation of the power supply voltage by using the measured fluctuation of the power supply voltage. In a case where analog/digital conversions of pixel signals are performed at different timings being not overlapped on a line basis, during a period, on the line basis, in which reading and analog/digital conversions are sequentially performed on the line basis, voltage of power supply to be supplied to associated pixels is sampled. The disclosure is applicable to solid-state imaging elements.

Solid-state imaging element, method of operating solid-state imaging element, imaging apparatus, and electronic device

To reduce influence occurring between signals simultaneously outputted from two pixels of the same pixel column via mutually different signal lines as much as possible. A solid-state imaging element including: a pixel column in which a plurality of pixels are juxtaposed in a column form; three or more juxtaposed signal lines each used for an output of a pixel included in the pixel column; and an A/D conversion section configured to convert an analog voltage outputted by the pixel to the signal line to a digital value. For a first pixel and a second pixel included in the pixel column, signal lines of connection destinations of these pixels are different from each other, and timings of outputs of analog voltages of these pixels to the signal lines coincide, an output from the first pixel to the signal line is permitted and an output from the second pixel to the signal line is disabled in a case where a prescribed number of one or more of signal lines or shield lines do not exist between the signal line that is a connection destination of the first pixel and the signal line that is a connection destination of the second pixel, and both outputs from the first pixel and the second pixel to the signal lines are permitted in a case where the prescribed number or more of signal lines or shield lines exist between the signal line that is a connection destination of the first pixel and the signal line that is a connection destination of the second pixel.

Solid-state imaging element and method for controlling solid-state imaging element

The present technology relates to an imaging element, an imaging method, and a piece of electronic equipment that permit faster processing. A column AD signal processing section and a ramp signal generation section are provided. The column AD signal processing section has, for each pixel column, an AD conversion section. The plurality of pixels arranged in the same column are connected to the AD conversion section via a vertical signal line. In parallel with reset operation or signal transfer operation, the pixel signals output from the pixels connected via other vertical signal lines are converted from analog to digital form by the AD conversion section. The ramp signal is supplied to the AD conversion sections that perform AD conversion of the pixel signals and is not supplied to the AD conversion sections that do not perform AD conversion. The present technology is applicable, for example, to CMOS image sensors.

Imaging element, imaging method, and electronic equipment

The present invention relates to a column A/D converter, column A/D conversion method, imaging device, and camera system that can reduce the amount of IR drop by dispersing the current consumed during the count operation, mitigate the counter characteristic degradation, readily reduce the amount of fluctuation in the power source voltage, and achieve operation at a low power source voltage. The column A/D converter includes a plurality of column processing units including an A/D conversion function, a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the column processing units, and a count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters.

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Fukuoka, Japan

Yuusuke Nishida