Hitachi, Ltd.

Hitachi Vantara Corporation

Yuusaku Kiyota

Hideaki Monji

Tomohiro Yoshihara

Takashi Nagao

Tomoyuki Kamazuka

Akira Yamamoto

Shoji Kato

Kenichi Betsuno

Shumpei Morita

Yoshihiro Toyohara

Tetsuhiro Gotou

Takeshi Hirao

Kenshiro Himoto

A compression-expansion control apparatus has a reconfiguration portion capable of configuring one or more compression circuits which compress data in plain text and/or one or more expansion circuits which expand the compressed data on a programmable logical circuit component, a waiting-time observing portion which observes processing waiting-time from when compression processing was requested till when the compression processing is started and processing waiting-time from when expansion processing was requested till when the expansion processing is started, a calculating portion which determines the number or a ratio of the compression circuits and the expansion circuits in the reconfiguration portion on the basis of the processing waiting-time of the compression processing and the processing waiting-time of the expansion processing, and a switching portion which executes reconfiguration of the compression circuit and/or the expansion circuit in the reconfiguration portion on the basis of the number or the ratio determined by the calculating portion.

Compression-expansion control apparatus, storage system, and compression-expansion control method

In a compression mode in which plaintext data is input, and compressed, a first code that is an error detection code is generated with respect to the plaintext data, and compressed. A circuit generates restored plaintext data in which the compressed data is decompressed, for confirming successfulness. A second code that is an error detection code is generated with respect to the restored plaintext data and is compared with the first code. In a case where the first code and the second code agree, the compressed data and the first or second code are output. In a decompression mode, plaintext data is generated in which the input compressed data is decompressed. A third code that is an error detection code is generated with respect to the plaintext data and is compared with an input code, and when the input code and the third code agree, the plaintext data is output.

Compression/decompression apparatus, storage system, and compression/decompression method

The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.

Storage device and data processing method

A storage system that can achieve a cryptographic operation circuit that supports multiple types of cryptographic operation formats. The cryptographic operation circuit is provided that encrypts data according to the format determined by the processor based on a request by the host terminal for writing the data into the storage device, and decrypts the encrypted data on the data stored in the storage device according to the format determined by the processor based on a request by the host terminal for reading the data from the storage device.

Storage system and cryptographic operation method

Provided is a storage system including a plurality of controllers. The storage system adopts a write-once data storage system and can implement high Input/Output (I/O) processing performance while ensuring data consistency when a failure occurs. Before metadata duplication, recovery data including information necessary for performing roll forward or roll back is stored in each controller, and then the metadata duplication is performed. A recovery data storage processing and the metadata duplication are offloaded to a hardware accelerator.

Storage system and control method of storage system including a storage control unit that performs a data amount reduction processing and an accelerator

A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.

Storage system and input and output control method

Encryption is enabled at a low load in a storage system. An encryption processing deviceuses, as an expectation value for key validation, a value that is uniquely identified from a storage location address of encrypted text data in a storage drive. The encryption processing deviceencrypts the expectation value and plain text data, respectively, using a same encryption key, substitutes a DIF according to the encrypted text data obtained by encrypting the plain text data, and stores the encrypted expectation value in the substituted DIF. Upon receiving a read request of the encrypted text data, the encryption processing devicedecrypts the encrypted expectation value stored in the substituted DIF using a decryption key, and validates whether the encryption key and the decryption key are properly corresponding by comparing the decrypted expectation value and the expectation value identified from the address at the time of reading.

Storage system and encryption processing method

A compression engine calculates replacement CRC codes, in predetermined data lengths, for DIF-in cleartext data including cleartext data and multiple CRC codes based on the cleartext data. The compression engine generates headered compressed-text data in which a header including the replacement CRC codes is added to compressed-text data in which the cleartext data is compressed, and generates code-in compressed-text data by calculating multiple CRC codes based on the headered compressed-text data to add the calculated CRC codes to the headered compressed-text data.

Data compression apparatus and data compression method

Storage system and control method of storage system

In a cryptographic apparatus, a cryptographic module executes first assurance check processing, which is processing for satisfying a predetermined certification requirement on image data of first software, and also executes second assurance check processing, which is processing for satisfying the above predetermined certification requirement on a verification target, which is at least part of image data of second software, and on which verification for satisfying the predetermined certification requirement is not performed by a device.

Cryptographic apparatus and self-test method of cryptographic apparatus

A data transfer system including a first memory and a processor includes a second memory and a DMA controller. The processor performs RMW on data which has a size less than a cache line size and in which a portion of a cache line (a unit area of the first memory) is a write destination. Output target data is transferred from an I/O device to the second memory. Thereafter, the DMA controller transfers the output target data from the second memory to the first memory in one or a plurality of transfer unit sizes by which the number of occurrences of RMW is minimized.

Data transfer system

A computer system comprises: a host computer including a host memory and a plurality of host processors; a storage apparatus; and an interface device coupled to the host computer and the storage apparatus, the interface device including a plurality of communication processors, wherein the host computer is configured to create a first logical partition, which is a destination of dedicated allocation of a first host memory area which is a partial area of the host memory, at least one of the plurality of host processors, and at least one of the plurality of communication processors.

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Tokyo, Japan

Yuusaku Kiyota