Panasonic Intellectual Property Management Co., Ltd.

Yuuki Soga

Takao Yamaguchi

Atsushi Yoshida

Tomoki Ishii

Satoru Tokutsu

A bus control device () includes a storage () that stores a transmission order of data pieces transmitted from a first node () to each second node (); a sorter () that receives data pieces transferred from each second node toward the first node and refers to a predefined sorting rule to determine a sorting destination of each data piece; a buffer () that stores the sorted data pieces while classifying the sorted data pieces by the second node as a transmission source; and a connection controller () that refers to change permission/rejection information indicating whether or not an order is permitted to be changed while the data piece is transferred from each second node to the first node, and transmits data pieces, the order of which is not changed, from the buffer to the first node in the same order as the transmission order stored on the storage.

Bus control device, relay device, and bus system

An exemplary interface apparatus includes: a header generator which receives, in a first order, a plurality of request headers extracted from a plurality of request packets, generates response headers associated with the request headers, and then stores the response headers so that the response headers are read in the first order; and a header order controller which controls the header generator so that if the plurality of request data have been transmitted to the memory in a second order, the respective response headers are read in the second order.

Interface apparatus and memory bus system

In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.

Bus interface apparatus, router, and bus system including them

In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route.

Growing community of inventors

Kyoto, Japan

Yuuki Soga