Fujitsu Corporation

Yuuki Ogata

Toshihiko Mori

Yoichi Koyanagi

Takashi Shiraishi

Hirotaka Tamura

Yasufumi Sakai

Ali Sheikholeslami

Joshua Liang

An optical transmitting device includes a plurality of transmitters configured to be arranged so as to correspond to a plurality of channels, the transmitters each reproducing a clock from an input data signal, and outputting the data signal identified and reproduced based on the reproduced clock to a light emitting element and a processor configured to control phase difference between the output data signals based on a result of comparison between phases of the reproduced clocks.

Optical transmitting device and optical receiving device

A frequency characteristic adjustment circuit is disclosed. The frequency characteristic adjustment circuit is disposed between an optical circuit element and a drive circuit for driving the optical circuit element. A capacitor is connected to an output of the drive circuit. A current supply circuit is controlled by a voltage generated by the drive circuit. The current supply circuit supplies a different current value depending on a voltage received from the drive circuit to the optical circuit element.

Frequency characteristic adjustment circuit, optical transmission module using the same, and optical transceiver

A serial-parallel conversion circuit includes: a phase detector that outputs a first phase detection signal indicating whether a phase of a clock signal is advance or behind, a signal amplifying circuit that amplifies the first phase detection signal with a gain so as to output a second phase detection signal; a control loop that adjusts the phase of the clock signal based on the second phase detection signal; an autocorrelation circuit that generates an autocorrelation value based on the first phase detection signal and a set delay amount, and outputs an autocorrelation signal indicating the autocorrelation value; a gain adjusting circuit that adjusts the gain in such a manner that the autocorrelation value matches a target correlation value; and a delay-amount determination circuit that sets a delay amount corresponding to a peak value of an obtained autocorrelation value obtained when the autocorrelation value changes in an oscillatory manner.

Clock generating circuit, serial-parallel conversion circuit, and information processing device

There is provided a driver circuit including a variable current-source configured to include, a first current-source coupled to a first input node to which a first signal is input from an external, a second current-source coupled to a second input node to which a second signal as an inversion of the first signal is input from the external, a first bypass circuit coupled between the first current-source and the first input node, the first bypass circuit being switched according to the second signal, and a second bypass circuit coupled between the second current-source and the second input node, the second bypass circuit being switched according to the first signal, and a terminal circuit configured to be terminated for an optical device driven by a drive signal according to the first signal, the drive signal being output from an output node coupled between the terminal circuit and the variable current-source.

Driver circuit, optical transmission module and optical transmission device

Disclosed is a frequency characteristic adjusting circuit disposed between an optical circuit element and a drive circuit driving the optical circuit element. The frequency characteristic adjusting circuit includes a capacitor, and two or more series circuits having a resistor and a switch, the two or more series circuits being connected in parallel with the capacitor, where resistance with respect to the switch that is turned on is changed according to an output voltage of the drive circuit by changing ON or OFF of the switch such that electric charge at a contact point between the optical circuit element and the capacitor is adjusted to be constant regardless of the output voltage of the drive circuit.

Frequency characteristic adjusting circuit, optical transmitter, and optical transceiver

A transmitting circuit includes: a multiplexer configured to output a third digital signal obtained by alternately synthesizing a first digital signal of a predetermined cycle length and a predetermined data rate with a second digital signal of the predetermined cycle length and the predetermined data rate; a first selector configured to output the first digital signal in a first state and output the third digital signal in a second state that is different from the first state; a second selector configured to output the second digital signal in the first state and output the third digital signal in the second state; a first driver circuit configured to output a signal corresponding to a signal output from the first selector; and a second driver circuit configured to output a signal corresponding to a signal output from the second selector.

Transmitting circuit, communication system, and communication method

A parallel-serial conversion circuit including a data transmission unit to output first data and second data of a prescribed pattern in accordance with a second clock obtained by dividing a first clock, a first flip flop to receive the first data so as to output the first data in accordance with the first clock, a second flip flop to receive the second data so as to output the second data in accordance with the first clock, a selector to select one of the first data and the second data so as to output the selected data in accordance with the first clock, and an adjustment unit to compare the second data to be received by the second flip flop and the first data output from the first flip flop so as to adjust, based on a comparison result, a timing for the first flip flop to receive the first data.

Parallel-serial conversion circuit, information processing apparatus and timing adjustment method

A timing control circuit includes a first variable-delay circuit, a multiplexer, a second variable-delay circuit, a decision circuit, and a control circuit. The first variable-delay circuit receives first data having a first communication speed and delays the first data by a variable delay. The multiplexer receives a first variable-delay circuit output and converts, based on a first control signal, the first data into second data having a second communication speed different from the first communication speed. The second variable-delay circuit receives third data having the first communication speed, and delays the third data by another variable-delay corresponding to the variable-delay of the first variable-delay circuit. The decision circuit compares a second variable-delay circuit output phase and a first control signal phase. The control circuit controls the variable-delay of the first variable-delay circuit and the another variable delay of the second variable-delay circuit based on decision circuit comparison.

Timing control circuit

A receiving circuit includes: a first decision circuit to output boundary data obtained by performing a binary-decision on input data in synchronization with a first clock; a first decision feedback equalizer to output center data obtained by performing equalization and a binary-decision on the input data using a first equalization coefficient in synchronization with a second clock; a phase detection circuit to detect phase information of the input data based on the boundary data and the center data; a phase control circuit to output phase difference information of the center data based on an opening of an eye pattern formed by overlaying data transition patterns; a first phase adjustment circuit to adjust a phase of the first clock based on the phase information; and a second phase adjustment circuit to adjust a phase of the second clock based on the phase information and the phase difference information.

Receiving circuit and data decision method

A latch circuit switches a differential operation performed by a differential operation circuit including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal. The latch circuit performs an operation to output an input signal and an inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation, according to a clock signal and an inverted clock signal.

Latch circuit, flip-flop circuit, and divider

A semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal (I) and a data signal that is output from another semiconductor circuit for testing.

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Kawasaki, Japan

Yuuki Ogata