Nec Electronics Corporation

Yuuji Torige

Satoshi Yamamoto

Atsushi Nakagawa

Hideo Inaba

Takuya Hirota

Susumu Takano

Masahiro Yoshida

Noriaki Komatsu

Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/Fis set by a one shot pulse from an OS circuit, a memory access request is inputted to a memory accessing pulse generator circuitthrough a NOR gate, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gateduring the memory access, the output of the NOR gateis at the 'L' level, and the refresh request is blocked by the AND gate. Thereafter, at the time when the latch control signal LC is turned into the 'L' level, F/Fsandare reset, the output of the NOR gateis turned into the &#x201c;H&#x201d; level, the refresh request is inputted to a refreshing pulse generator circuit, and a refresh enable signal RERF is outputted.

Semiconductor storage device and refresh control method thereof

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Kanagawa, Japan

Yuuji Torige