Kabushiki Kaisha Toshiba

Yuuichi Tatsumi

Hiroshi Iwahashi

Hidenobu Minagawa

Masamichi Asano

Mizuho Imai

Hideo Kato

Hiroto Nakai

Toshifumi Minami

Kiyomi Naruke

Takafumi Ikeda

Yoshio Mochizuki

Takahito Nakazawa

Hideaki Maekawa

Hitoshi Ohta

Noriaki Suzuki

Yasumasa Sawada

Minoru Kurata

Kazuhiko Satou

A semiconductor device has a circuit element region formed on a semiconductor substrate, and a protective pattern formed so as to surround the circuit element region. The protective pattern comprises a first element separation region formed on the semiconductor substrate, a second element separation region formed on the semiconductor substrate and having a width smaller than that of the first element separation region, a first element region formed between the first element separation region and the second element separation region, a first gate layer formed on the first element separation region, a wiring layer formed on the first gate layer, a passivation layer formed above the wiring layer, a second element region, an insulation film formed on the second element region, and a second gate layer formed on the insulation film, the first element separation region, the first element region, the second element separation region and the second element region being located in this order from the nearer side of the circuit element region.

Semiconductor device having a protection pattern with two element separation regions

A method for manufacturing an industrial product encompasses: forming a intermediate product pattern, which implements a part of a intermediate product of the industrial product by a sequence of processes corresponds to a part of a procedure for manufacturing the industrial product; forming an interconnect-changing insulator on the intermediate product pattern; boring sampling contact holes in the interconnect-changing insulator so as to make bare a part of the intermediate product pattern to define sampling sites; delineating evaluation interconnects on the interconnect-changing insulator so that each of the evaluation interconnects can electrically connected to at least one of the sampling sites of intermediate product pattern; and measuring an electrical resistance between subject sampling sites through the evaluation interconnects so as to detect a product defect in the intermediate product pattern.

Method for manufacturing industrial products and combination of masks for manufacturing the same

There is disclosed a memory cell which has a diffusion layers constituting source/drain areas formed on a p-type silicon substrate surface, and a channel area formed between the diffusion layers. Above the channel area, an insulating film of a laminated structure is formed of a silicon oxide film, a silicon nitride film and a silicon oxide film. A gate electrode is formed on the upper surface of the insulating film of the laminated structure. The gate electrode is used as a word line. Moreover, an interlayer insulating film is formed between the diffusion layer and the gate electrode. By injecting hot electrons from the substrate to the silicon nitride film in the insulating film of the laminated structure, data is written. The silicon nitride film and the diffusion layer are partially overlapped in a vertical direction, and an offset portion is disposed between the silicon nitride film and the diffusion layer.

Method for manufacturing a semiconductor memory device with a fine structure

That surface portion of a semiconductor substrate which is adjacent to a buried source region formed in the substrate is covered with an offset side wall to suppress expansion of a channel beneath the offset side wall. In addition, buried source regions in the form of offset side walls are formed on the two sides of a drain region having one non-offset side wall to prevent a write or read error in unselected memory cell transistors on both sides of a selected memory transistor either in a data write or in a data read.

Semiconductor memory device using MONOS type nonvolatile memory cell

Cryptographic key data and data subjected to an operation by use of the cryptographic key data are previously stored in a memory cell array. A memory cell in which the cryptographic key data is stored is accessed and latched and the cryptographic key data is latched in a latch circuit before read out data from the memory cell array. After this, the latched data and data output from a sense amplifier are subjected to an operation by an arithmetical circuit to decode the data and the result of the operation is output as readout data.

Semiconductor memory device having copy protect function and method for

A data transfer control circuit is connected between a sense amplifier and output buffer circuit. The data transfer control circuit is controlled by a pulse signal supplied from a pulse signal generator so as to have longer delay time which pulse signal is not generated by the pulse signal generator, and operate as noise canceller and prevents from outputting erroneous signal therefrom to the output buffer circuit.

Semiconductor integrated circuit

In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Nonvolatile semiconductor memory device

A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.

Semiconductor memory device having transfer gates which prevent high

Nonvolatile semiconductor memory device with stabilized data write

A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.

Semiconductor memory device having a test cell array

A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.

High voltage booster circuit for use in EEPROMs

A semiconductor integrated circuit includes an output circuit and a control circuit for controlling the output circuit. The control circuit controls the output circuit so as to charge or discharge a preset node in the output circuit at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal has been changed in level.

Output circuit of semiconductor integrated circuit device

A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.

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Tokyo, Japan

Yuuichi Tatsumi