Fujitsu Corporation

Nec Lcd Technologies, Ltd.

Nlt Technologies, Ltd.

Yuuichi Hasegawa

Hidetake Suzuki

A DC/AC inverter substrate includes a voltage abnormality detector circuit. All of a high voltage side detection sensor, a low voltage side detection sensor, and a high-voltage and low-voltage detection sensor in the voltage abnormality detector circuit are disposed without being electrically connected to a secondary side of a transformer or to a connection point. Those detection sensors are not damaged since overvoltage is not applied to the voltage abnormality detector circuit when abnormal discharge occurs because the detection sensors are not electrically connected.

DC/AC inverter substrate having voltage abnormality detector circuit

A plurality of individually retractable racks on which a single module is mounted on each rack is disposed on the upper and middle tiers of a portable carriage main body. Provided to the lower tier of the carriage main body are a operating panel for setting work content and conditions; a signal source for selectively outputting a circuit adjustment signal, an aging testing signal, and a display inspection signal; a power supply for circuit adjustment, a power supply for aging testing, and a power supply for display inspection; and an output unit for selecting an operation from circuit adjustment, aging testing, and display inspection on the basis of the work content and work conditions that have been input in the operating panel, and feeding the power and signals for the selected operation to the modules.

Carriage for liquid crystal module

A field effect transistor including a gate electrode divided into a plurality of parts in the gate-length direction. The gate electrode makes Schottky-contacts with a semiconductor layer or is formed on the semiconductor layer through a gate insulating film.

Method of making field effect transistor for high-frequency operation

A field effect semiconductor device which restricts current flow through a drain-gate path, but allows current to easily flow through a gate-source path. A high potential barrier layer is formed on the drain side of an active layer. The potential barrier layer has a wider energy band gap than the active layer. A source electrode and a drain electrode make ohmic contact with the active layer and a gate electrode exists between the source electrode and the drain electrode. The gate electrode is partially formed on the potential barrier layer and makes Schottky contact with the active layer on the source side of the semiconductor device and makes Schottky contact with the potential barrier layer on the drain side of the semiconductor device.

Heterojunction FET with a high potential barrier layer and gate structure

A method of producing a compound semiconductor device comprises the steps of: forming a recess portion on a compound semiconductor substrate; forming an ion penetrating mask on the recess portion in such a manner that the surfaces of the compound semiconductor substrate and the ion penetrating mask are level; forming an active layer having a substantially uniform depth is the compound semiconductor by implanting impurity ions into the entire exposed surface and, removing the ion penetrating mask and forming a gate electrode at the recess portion.

Growing community of inventors

Kawasaki, Japan

Yuuichi Hasegawa