Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Yuui Shimizu

Yoshihisa Iwata

Yoshinao Suzuki

Koji Kato

Kenji Tsuchida

Yoshihiko Kamata

Tsukasa Kobayashi

Yasuhiro Suematsu

Yuki Shimizu

Hideyuki Kataoka

Takumi Fujimoto

Masaru Koyanagi

Tatsuya Kishi

Takuya Futatsuyama

Shigeo Ohshima

Mie Matsuo

Masami Masuda

Junya Matsuno

Satoshi Inoue

Yuko Namiki

Kazuyoshi Muraoka

Masatoshi Kohno

Haruki Toda

Tsuneo Inaba

Kentaro Nakajima

Katsuyuki Fujita

Toshiaki Edahiro

Masayuki Sagoi

Tomofumi Fujimura

Masahiro Hosoya

Taichi Wakui

A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Semiconductor memory device

A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.

Semiconductor storage device

According to one embodiment, the amplifier circuit includes a first and second differential amplifier. The first differential amplifier includes first and second transistors, a first current source, and a second current source that is configured to supply a current to the first and second transistors via a first switch element. The second differential amplifier includes third and fourth transistors, a third current source, and a fourth current source that is configured to supply a current to the third and fourth transistors via a second switch element. A first signal is input to the first and third transistors. The first switch elements are controlled by third and fourth signals, respectively. The third signal and the fourth signal are complementary.

Amplifier circuit

According to one embodiment, an electrostatic discharge semiconductor device includes one or more wiring layers first disposed over a substrate, including: a wiring electrically connected at a first connecting point of a pad, a second wiring electrically connected at a second connecting point of a ground wiring, and a third wiring electrically connected at a third connecting point of the ground wiring; a first transistor formed in the substrate comprising a first diffusion region electrically connected to the first wiring, a second diffusion region electrically connected to the second wiring, and a gate electrically connected to the ground wiring; and a second transistor formed in the substrate comprising the first diffusion region electrically connected to the first wiring, a third diffusion region electrically connected to the third wiring, and a gate electrically connected to the ground wiring, wherein, a first resistance value of a first current pathway leading from the first connecting point to the second connecting point via the first transistor is different from a second resistance value of a second current pathway leading from the first connecting point to the third connecting point via the second transistor.

Semiconductor device

According to one embodiment, a semiconductor integrated device includes a first node that receives a first voltage, a second node that receives a second voltage, and an electrode. A PMOS transistor is coupled between the first node and the electrode. An NMOS transistor is coupled between the second node and the electrode. A control signal at a voltage lower than the second voltage is supplied to a gate electrode of the PMOS transistor. A control signal at a voltage higher than the first voltage is supplied to a gate electrode of the NMOS transistor.

Semiconductor integrated device

A semiconductor device comprises a plurality of semiconductor chips stacked on a substrate. The semiconductor chip comprises: an internal power supply voltage generating circuit that generates an internal power supply voltage based on an external power supply; a power supply line that supplies the internal power supply voltage; an internal power supply pad connected to the power supply line; and a stabilizing capacitance connected to the power supply line. The internal power supply pad is electrically short-circuited with the internal power supply pad included in another semiconductor chip.

A semiconductor memory device comprises: a plurality of on-die termination circuits connected to each of a plurality of input/output pads; and a control circuit for controlling the on-die termination circuit. The on-die termination circuit comprises: a pull-up element connected between a first terminal and an output terminal; and a pull-down element connected between the output terminal and a second terminal. The pull-up element is driven by a first pull-up element driver, and the pull-down element is driven by a first pull-down element driver. The control circuit activates a plurality of the on-die termination circuits at different timings.

A semiconductor memory device comprises a first-supplied-voltage-supplying pad, a second-supplied-voltage-supplying pad, a data input/output pad, a memory body, a buffer circuit and an impedance-controlling circuit. A first supplied voltage is supplied to the memory body. A second supplied voltage is supplied to the buffer circuit. The impedance-controlling circuit controls an impedance of the buffer circuit on a side connected to the data input/output pad. The semiconductor memory device comprises a voltage-generating circuit generating a first inner voltage. The impedance-controlling circuit comprises a first P-channel transistor. A source terminal of the first P-channel transistor is connected to the first-supplied-voltage-supplying pad, and the first inner voltage generated from the voltage-generating circuit is selectively supplied to a gate terminal of the first P-channel transistor.

Semiconductor memory device and method of testing the same

According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor.

Interface circuit

According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

Level shift circuit

According to one embodiment, a memory system includes a first semiconductor memory and a controller. The first semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock. The controller includes a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory. The controller also includes an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit.

Memory system

According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor.

Output buffer

A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits.

Growing community of inventors

Yokohama, Japan

Yuui Shimizu