International Business Machines Corporation

Yutong Wu

Richard Paul Volant

Bradley Paul Jones

Sameer T Shikalgar

Michael J Toner

Yunsheng Song

Cuc Kim Huynh

James M Rice

Gary L Milo

Douglas P Nadeau

Paul A Manfredi

Kenneth A Bandy

Thomas J Martin

Stuart D Cheney

Brad J Rawlins

Neil A Reitmeyer

Sean M Dickinson

A method of optimizing production cycle queue time includes selecting a plurality of process steps for a production cycle, calculating queue times for each of the plurality of process steps, statistically analyzing the queue times, and generating at least one visual output that illustrates the statistically analyzed queue times.

Method of optimizing queue times in a production cycle

Methods, systems, and computer program products for managing movement of work-in-process materials between processing units in an automated manufacturing environment are provided. A system includes a host system in communication with a work-in-process (WIP) material lot. The system also includes an application executing on the host. The application implements a method that includes tracking a position of the WIP material lot, receiving a list of the processing units designated to be inoperative during a down time, and receiving a start time and a duration of the down time. The method also includes determining a maximum dwell time for each of the designated processing units and scheduling movement of the WIP material lot during an interim between a current time and the start time of the down time based on current position of the work-in-process material lot, the current time, the start time and duration of the down time, and the maximum dwell time.

Methods, systems, and computer program products for managing movement of work-in-process materials in an automated manufacturing environment

Controlling stocker capacity in an automated facility and controlling monitor budgets by capped releases, capped FOUP supplies, and wafer reuse methodology. A Database is used to order, track, and reclaim test (monitor) wafers in the FAB. The database automatically controls the amount of FOUPs in the FAB as well as the amount of wafers released into the FAB each day. This database also interacts with the Control Center in helping to release monitor wafers in the FAB.

Monitor wafer purchase and controls database

The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer is deposited on the raised and recessed regions of the semiconductor substrate A selectively removable filler layer is then deposited on the FET protection layer with a thickness to over-fill the recessed regions of the gates of the FETs. The selectively removable filler layer is then planarized until the FET protection layer on top of the gates is exposed. The recessed regions between the gates are left substantially filled with selectively removable filler layer The selectively removable filler layer in the region where the BJT is formed is patterned and an opening is made to allow for the depositing of layers of different materials used in the construction of the BJT. The layer of different materials are processed by methods known in the art to form polysilicon emitter of the BJT. Due to selectively removable filler layer creating a substantially planar surface in the recessed regions of the FETs, little to none of the layers of different materials that are used in the construction of the BJT are deposited within the recessed regions Thus, removal of the layers of different materials ( &prime;), from the FET region is simplified. After removal of the layers of different materials ( &prime;), from the FET region, the selectively removable filler layer is removed selectively to the FET protection layer The FET protection layer is then removed. The recessed regions between the gates of the FETs are free from residual films.

Selectively removable filler layer for BiCMOS process

An apparatus and method of planarizing objects, particularly electronic components. The off-concentric polishing system of the present invention comprises at least two polishing platens positioned adjacent each other such that the polishing portions of the platens are substantially co-planar. At least one wafer carrier is moveably mounted over the at least two platens such that a wafer may be polished by more than one platen substantially simultaneously. The platen configurations may be in a linear or non-linear configuration such that the wafer being polished is no longer centrally disposed over a single platen but is off-concentrically positioned over multiple platens. The off-concentric positioning of the wafer provides enhanced slurry distribution and endpoint detection. The present invention reduces time and cost in manufacturing electronic components by engaging several polishing conditions simultaneously without the need for sequential polishing.

Off-concentric polishing system design

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Hopewell Junction, NY, United States of America

Yutong Wu