Mitsubishi Denki Kabushiki Kaisha

Yuto Ikeda

Hideto Hidaka

Masaki Kumanoya

Hideshi Miyatake

Hiroyuki Yamasaki

Yasuhiro Konishi

Katsumi Dosaka

Kazuhiro Tsukamoto

Masaki Shimoda

Koichiro Mashiko

Tadato Yamagata

Yoshikazu Morooka

Takeshi Kajimoto

Yoshinori Inoue

Yuichiro Komiya

Jun Nakai

Tetsushi Hoshita

Konishi Yasuhiro

A precharge control circuit controls on/off of transfer gates to set a signal level of a precharge control signal in accordance with a level of a control signal input to a precharge command input pad when a write recovery test signal is active. In a normal operation, the precharge control circuit deactivates the write recovery test signal to set the signal level of the precharge control signal in accordance with a combination of control signals. Consequently, the precharge operation can be started in accordance with an arbitrary control signal generated by an external memory tester or the like in a test mode, and thereby evaluation of a write recovery time can be executed.

Semiconductor device allowing efficient evaluation of fast operation

A semiconductor memory device comprising a plurality of word lines that come in two types: ordinary word lines planned to be used ordinarily, and redundant word lines to be used to replace any ordinary word line judged faulty. Boosting transistors are incorporated to boost all bit lines forcibly to a supply voltage. When the bit lines are brought to the supply voltage while the word lines are connected to ground, a memory cell may be found written with data represented by the supply voltage on the bit lines. This reveals a short-circuit between a bit line and the word line corresponding to the memory cell. The short-circuited word line is then replaced by a redundant word line.

Semiconductor memory device and methods for inspecting and manufacturing

A reference voltage generating circuit of a DRAM includes a current mirror circuit constituted of first to fourth transistors. The gate of the third transistor is connected to the source of a fifth transistor. When a zero-power on reset signal, which becomes L on turn-on of the power supply, and becomes H after a predetermined period, is applied to the gate of the fifth transistor, and an external power supply voltage is forced to be applied to the gate of the third transistor on turn-on of the power supply, a reference voltage following the rise of the external power supply voltage is provided from the output of the current mirror circuit.

Reference voltage generating circuit of semiconductor memory device

The present invention relates to a memory device having reduced access time of memory cells in a test mode. The memory device forms, in the test mode, read data D.sub.R by applying Ex-OR processing to a plurality of data read from a memory cell array 11 by a data processing circuit 5, to provide the formed data to the outside through a data output circuit 6. The timing of the output of data to the outside is delayed, by delay circuit 12 in the test mode, than that in the normal operation by a time period corresponding to time required for the EX-OR processing in data processing circuit 5. Consequently, output of invalid data to the outside can be prevented, and thus access time of valid data can be reduced.

Memory device delaying timing of outputting data in a test mode as

A semiconductor memory device with two memory cell arrays. Memory cell arrays are commonly provided with a group of sense amplifiers. Each sense amplifier of a group of sense amplifiers is connected to a corresponding bit line pair within one memory cell array through a transmission transistor pair formed of N channel MOS transistors, and connected to a corresponding bit line pair within the other memory cell array through a transmission transistor pair formed of P channel MOS transistors. The same control signals are applied to gates of these transmission transistor pairs. The control signals maintain 1/2.multidot.Vcc level during a precharge period, and rise to high levels or fall down to low levels.

Shared sense amplifier type semiconductor memory device

A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Dynamic random access memory with read-write signal of shortened duration

A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Dynamic random access memory

A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

Semiconductor memory device with address transition detection and timing

A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals '0'. The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals '1'. A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.

Redundary circuit with a spare main decoder responsive to an address of

A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

Dynamic random access memory device having an improved timing arrangement

A spare Y decoder is provided with MOS transistors 14 and 20 for charge on both sides of a parasitic resistor 19. As a result, nodes N1 and N2 are rapidly charged by the MOS transistors 20 and 14 for charge, respectively.

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Hyogo, Japan

Yuto Ikeda